74AHCT2G00DP,125 Nexperia

74AHC2G00 74AHCT2G00 Dual 2-input NAND gate Rev. 5 7 March 2019 Product data sheet 1. General description The 74AHC2G00 74AHCT2G00 are high-speed Si-gate CMOS devices. They provide two 2-input NAND gates. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features and benefits Symmetrical output impedance High noise immunity ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Low power dissipation Balanced propagation delays Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC2G00DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74AHC2G00DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74AHCT2G00DC 4. Marking Table 2. Marking Type number Marking code 1 74AHC2G00DP A00 74AHC2G00DC A00 74AHCT2G00DC C00 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code.Nexperia 74AHC2G00 74AHCT2G00 Dual 2-input NAND gate 5. Functional diagram & 1A 1Y 1B 2A & 2Y 2B 001aah748 001aah749 Fig. 1. Logic symbol Fig. 2. IEC logic symbol B Y A mna099 Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74AHC2G00 74AHCT2G00 1A 1 8 V CC 1B 2 7 1Y 3 6 2Y 2B 4 5 GND 2A 001aaj388 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output V 8 supply voltage CC 74AHC AHCT2G00 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 5 7 March 2019 2 / 11