74AUP1T98-Q100 Low-power configurable gate with voltage-level translator Rev. 3 9 December 2020 Product data sheet 1. General description The 74AUP1T98-Q100 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer using the 3-bit input. All inputs can be connected directly to V CC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire V range CC from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using I . The OFF I circuitry disables the output, preventing the potentially damaging backflow current through the OFF device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.3 V to 3.6 V High noise immunity ESD protection: MIL-STD-883, method 3015 Class 3A, exceeds 5000 V HBM JESD22-A114F Class 3A, exceeds 5000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Low static power consumption I = 1.5 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T98GW-Q100 -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 4. Marking Table 2. Marking Type number Marking code 74AUP1T98GW-Q100 aRNexperia 74AUP1T98-Q100 Low-power configurable gate with voltage-level translator 5. Functional diagram 3 A 4 Y 1 B 6 C 001aad987 Fig. 1. Logic symbol 6. Pinning information 6.1. Pinning 74AUP1T98 B 1 6 C GND 2 5 V CC A 3 4 Y 001aah839 Fig. 2. Pin configuration SOT363 6.2. Pin description Table 3. Pin description Symbol Pin Description B 1 data input GND 2 ground (0 V) A 3 data input Y 4 data output V 5 supply voltage CC C 6 data input 74AUP1T98 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 9 December 2020 2 / 13