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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.74LVX08 Low Voltage Quad 2-Input AND Gate
June 2014
74LVX08
Low Voltage Quad 2-Input AND Gate
Features Description
Input Voltage Level Translation from 5 V to 3 V The LVX08 contains four 2-input AND gates. The inputs
Ideal for Low-power / Low-Noise 3.3 V Applications tolerate voltages up to 7 V allowing the interface of 5 V
systems to 3 V systems.
Guaranteed Simultaneous Switching Noise Level and
Dynamic threshold Performance
Ordering Information
Part Number Top Mark Package Packing Method Packing Description
14-Lead Small Outline Integrated Circuit, JEDEC
74LVX08M LVX08 SOIC 14L Rail
MS-012, 0.150 inch Narrow
14-Lead Small Outline Integrated Circuit, JEDEC
74LVX08MX LVX08 SOIC 14L Tape and Reel
MS-012, 0.150 inch Narrow
14-Lead Thin Shrink Small Outline Package,
74LVX08MTCX LVX08 TSSOP 14L Tape and Reel
JEDEC MO-153, 4.4 mm Wide
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram Logic Symbol
IEEE/IEC
Pin Description
Pin Names Description
A , B Inputs
n n
O Outputs
n
1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVX08 Rev. 1.5.0 1