74LVX273SJ ON Semiconductor

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This literature is subject to all applicable copyright laws and is not for resale in any manner.74LVX273 Low Voltage Octal D-Type Flip-Flop June 1993 Revised April 2005 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with Input voltage translation from 5V to 3V individual D inputs and Q outputs. The common buffered Ideal for low power/low noise 3.3V applications Clock (CP) and Master Reset (MR) input load and reset Guaranteed simultaneous switching noise level and (clear) all flip-flops simultaneously. dynamic threshold performance The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transi- tion, is transferred to the corresponding flip-flops Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. Ordering Code: Order Number Package Number Package Description 74LVX273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX273SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending letter suffix X to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbols Connection Diagram IEEE/IEC Truth Table Operating Mode Inputs Outputs Pin Descriptions D Q MR CP n n Pin Names Description Reset (Clear) L X X L D D Data Inputs 0 7 Load '1' H HH MR Master Reset Load '0' H LL CP Clock Pulse Input H HIGH Voltage Level X Immaterial Q Q Data Outputs L LOW Voltage Level LOW-to-HIGH Transition 0 7 2005 Fairchild Semiconductor Corporation DS011614 www.fairchildsemi.com