74HCT374D Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT374 Octal D-type flip-flop positive edge-trigger 3-state December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Octal D-type ip-op positive 74HC/HCT374 edge-trigger 3-state FEATURES The 74HC/HCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state 3-state non-inverting outputs for bus oriented outputs for bus oriented applications. A clock (CP) and an applications output enable (OE) input are common to all flip-flops. 8-bit positive, edge-triggered register The 8 flip-flops will store the state of their individual Common 3-state output enable input D-inputs that meet the set-up and hold times requirements Independent register and 3-state buffer operation on the LOW-to-HIGH CP transition. Output capability: bus driver When OE is LOW, the contents of the 8 flip-flops are I category: MSI CC available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. GENERAL DESCRIPTION The 374 is functionally identical to the 534, but has The 74HC/HCT374 are high-speed Si-gate CMOS devices non-inverting outputs. and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay CP to Q C = 15 pF V = 5 V 15 13 ns PHL PLH n L CC f maximum clock frequency 77 48 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per ip-op notes 1 and 2 17 17 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2