74LV4052PW,118 Nexperia

74LV4052 Dual 4-channel analog multiplexer/demultiplexer Rev. 6 24 September 2021 Product data sheet 1. General description The 74LV4052 is a dual single-pole quad-throw analog switch suitable for use in 4:1 multiplexer/ demultiplexer applications. Each switch features four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E) and two digital select inputs (S0, S1) are common to both switches. When E is HIGH, the switches are turned off. Digital inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 to 6.0 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Optimized for low-voltage applications: 1.0 V to 6.0 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Low ON resistance: 145 (typical) at V - V = 2.0 V CC EE 90 (typical) at V - V = 3.0 V CC EE 60 (typical) at V - V = 4.5 V CC EE Logic level translation: To enable 3 V logic to communicate with 3 V analog signals Typical break before make built in Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4052D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LV4052PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mmNexperia 74LV4052 Dual 4-channel analog multiplexer/demultiplexer 4. Functional diagram V CC 16 13 1Z 12 1Y0 14 1Y1 15 1Y2 10 S0 11 1Y3 LOGIC 9 1-OF-4 S1 LEVEL DECODER CONVERSION 1 2Y0 6 E 5 2Y1 2 2Y2 4 2Y3 3 2Z 8 7 V EE GND aaa-008169 Fig. 1. Functional diagram 10 0 0 4 3 9 1 13 6 G4 1Z 1Y0 12 MDX 10 S0 1Y1 14 0 1 9 S1 1Y2 15 1 5 3 1Y3 11 2 2 2Y0 1 3 4 2Y1 5 12 2Y2 2 14 13 6 E 2Y3 4 15 2Z 11 001aah824 3 001aah825 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74LV4052 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 24 September 2021 2 / 18