74LVC86APW,112 Nexperia

74LVC86A Quad 2-input EXCLUSIVE-OR gate Rev. 6 19 August 2021 Product data sheet 1. General description The 74LVC86A is a quad 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to 125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC86AD -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC86APW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC86ABQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC86A Quad 2-input EXCLUSIVE-OR gate 4. Functional diagram 1 =1 3 2 4 =1 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B =1 8 10 9 3A 3Y 8 A 10 3B 12 12 4A Y =1 11 4Y 11 13 4B 13 B mna787 mna786 mna788 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram for one gate 5. Pinning information 5.1. Pinning 74LVC86A terminal 1 index area 1B 2 13 4B 1Y 3 12 4A 74LVC86A 2A 4 11 4Y 2B 5 10 3B (1) GND 1 14 1A V CC 6 9 2Y 3A 74LVC86A 1B 2 13 4B 1A 1 14 V 1Y 3 12 4A CC aaa-033854 1B 2 13 4B 2A 4 11 4Y Transparent top view 1Y 3 12 4A (1) This is not a ground pin. There 2A 4 11 4Y 2B 5 10 3B is no electrical or mechanical 2B 5 10 3B 2Y 6 9 3A requirement to solder the pad. In 2Y 6 9 3A case soldered, the solder land GND 7 8 3Y GND 7 8 3Y should remain floating or connected aaa-033852 aaa-033853 to GND. Fig. 4. Pin configuration Fig. 5. Pin configuration Fig. 6. Pin configuration SOT108-1 (SO14) SOT402-1 (TSSOP14) SOT762-1 (DHVQFN14) 74LVC86A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 19 August 2021 2 / 12 GND 7 1 1A 3Y 8 14 V CC