74LVC8T245 74LVCH8T245 8-bit dual supply translating transceiver 3-state Rev. 3 12 December 2011 Product data sheet 1. General description The 74LVC8T245 74LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (V and V ). Both V and V can be supplied at CC(A) CC(B) CC(A) CC(B) any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to V and pins Bn are referenced to V . A HIGH on DIR allows CC(A) CC(B) transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The devices are fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at CC(A) CC(B) GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a valid logic level. 2. Features and benefits Wide supply voltage range: V : 1.2 V to 5.5 V CC(A) V : 1.2 V to 5.5 V CC(B) High noise immunity Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 4000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Maximum data rates: 420 Mbps (3.3 V to 5.0 V translation) 210 Mbps (translate to 3.3 V)) 140 Mbps (translate to 2.5 V) 75 Mbps (translate to 1.8 V)74LVC8T245 74LVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver 3-state 60 Mbps (translate to 1.5 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78B Class II 24 mA output drive (V =3.0 V) CC Inputs accept voltages up to 5.5 V Low power consumption: 30 A maximum I CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC8T245PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74LVCH8T245PW 74LVC8T245BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1 thin quad flat package no leads 24 terminals 74LVCH8T245BQ body 3.5 5.5 0.85 mm 4. Functional diagram B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18 17 16 15 14 V V CC(A) CC(B) 22 OE 2 DIR 3 45678910 A1 A2 A3 A4 A5 A6 A7 A8 001aai472 Fig 1. Logic symbol 74LVC LVCH8T245 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 12 December 2011 2 of 28