74VHC08D,118 Nexperia

74VHC08 74VHCT08 Quad 2-input AND gate Rev. 2 8 April 2020 Product data sheet 1. General description The 74VHC08 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC08 74VHCT08 provide the quad 2-input AND function. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than V CC Input levels: The 74VHC08 operates with CMOS logic levels The 74VHCT08 operates with TTL logic levels ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC08D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74VHCT08D 74VHC08PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74VHCT08PW 74VHC08BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals 74VHCT08BQ body 2.5 3 0.85 mmNexperia 74VHC08 74VHCT08 Quad 2-input AND gate 4. Functional diagram 1 & 3 2 4 & 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B & 8 10 9 3A 3Y 8 10 3B A 12 12 4A & 11 4Y 11 Y 13 4B 13 B mna222 mna223 mna221 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74VHC08 74VHCT08 terminal 1 index area 74VHC08 74VHCT08 1B 2 13 4B 1Y 3 12 4A 1A 1 14 V CC 2A 4 11 4Y 1B 2 13 4B 5 10 2B (1) 3B GND 1Y 3 12 4A 2Y 6 9 3A 4 11 2A 4Y 2B 5 10 3B 001aak041 Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case 001aak040 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74VHC VHCT08 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 8 April 2020 2 / 13 GND 7 1 1A V 3Y 8 14 CC