74VHC08-Q100 74VHCT08-Q100 Quad 2-input AND gate Rev. 2 8 April 2020 Product data sheet 1. General description The 74VHC08-Q100 74VHCT08-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC08-Q100 74VHCT08-Q100 provide the quad 2-input AND function. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accept voltages higher than V CC Input levels: The 74VHC08-Q100 operates with CMOS logic levels The 74VHCT08-Q100 operates with TTL logic levels ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC08D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74VHCT08D-Q100 74VHC08PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74VHCT08PW-Q100 74VHC08BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74VHCT08BQ-Q100 14 terminals body 2.5 3 0.85 mmNexperia 74VHC08-Q100 74VHCT08-Q100 Quad 2-input AND gate 4. Functional diagram 1 & 3 2 4 & 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B & 8 10 9 3A 3Y 8 10 3B A 12 12 4A & 11 4Y 11 Y 13 4B 13 B mna222 mna223 mna221 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74VHC08-Q100 74VHCT08-Q100 terminal 1 index area 74VHC08-Q100 74VHCT08-Q100 1B 2 13 4B 1Y 3 12 4A 1A 1 14 V CC 2A 4 11 4Y 1B 2 13 4B 5 10 2B (1) 3B GND 1Y 3 12 4A 2Y 6 9 3A 4 11 2A 4Y 2B 5 10 3B aaa-009733 Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case aaa-009732 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74VHC VHCT08 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 8 April 2020 2 / 13 GND 7 1 1A V 3Y 8 14 CC