74AHCT240D,112 NXP

74AHC240 74AHCT240 Octal buffer/line driver inverting 3-state Rev. 4 25 September 2013 Product data sheet 1. General description The 74AHC240 and 74AHCT240 are 8-bit inverting buffer/line drivers with 3-state outputs. These devices can be used as two 4-bit buffers or one 8-bit buffer. They feature two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are over voltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than V CC For 74AHC240 only: operates with CMOS input levels For 74AHCT240 only: operates with TTL input levels ESD protection: HBM JESD22-A114F exceeds 2000 V CDM JESD22-C101D exceeds 1000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC240D 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHCT240D 74AHC240PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74AHCT240PW 74AHC240BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals 74AHCT240BQ body 2.5 4.5 0.85 mmNXP Semiconductors 74AHC240 74AHCT240 Octal buffer/line driver inverting 3-state 4. Functional diagram 1 EN 18 2 4 16 2 1A0 1Y0 18 14 6 17 2A0 2Y0 3 12 8 4 1A1 1Y1 16 15 2A1 2Y1 5 19 EN 6 14 1A2 1Y2 13 2A2 2Y2 7 11 9 8 1A3 1Y3 12 13 7 11 9 2A3 2Y3 5 15 1OE 17 3 1 19 2OE mgu779 mgu778 Fig 1. Logic symbol Fig 2. IEC logic symbol 5. Pinning information 5.1 Pinning 74AHC240 74AHCT240 terminal 1 index area 74AHC240 2 19 1A0 2OE 74AHCT240 2Y0 3 18 1Y0 1OE 1 20 V CC 1A1 4 17 2A0 1A0 2 19 2OE 2Y1 5 16 1Y1 2Y0 3 18 1Y0 1A2 6 15 2A1 1A1 4 17 2A0 2Y1 5 16 1Y1 7 14 2Y2 1Y2 1A2 6 15 2A1 (1) 1A3 8 13 2A2 GND 2Y2 7 14 1Y2 2Y3 9 12 1Y3 1A3 8 13 2A2 2Y3 9 12 1Y3 001aal193 GND 10 11 2A3 001aal192 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. Pin configuration SO20 and TSSOP20 Fig 4. Pin configuration DHVQFN20 74AHC AHCT240 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 25 September 2013 2 of 16 GND 10 1 1OE 2A3 11 20 V CC