74AUP1Z125GS NXP

74AUP1Z125 Low-power X-tal driver with enable and internal resistor 3-state Rev. 5 8 August 2012 Product data sheet 1. General description The 74AUP1Z125 combines the functions of the 74AUP1GU04 and 74AUP1G125 with enable circuitry and an internal bias resistor to provide a device optimized for use in crystal oscillator applications. When not in use the EN input can be driven HIGH, pulling up the X1 input and putting the device in a low-power disable mode. Schmitt trigger action at the EN input makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to CC 3.6 V. This device is fully specified for partial power-down applications using I at output Y. OFF The I circuitry disables the output Y, preventing the damaging backflow current through OFF the device when it is powered down. The integration of the two devices into the 74AUP1Z125 produces the benefits of a compact footprint, lower power dissipation and stable operation over a wide range of frequency and temperature. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation at output Y OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP1Z125 NXP Semiconductors Low-power X-tal driver with enable and internal resistor 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1Z125GW 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1Z125GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1Z125GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP1Z125GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1Z125GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP1Z125GW 55 74AUP1Z125GM 55 74AUP1Z125GF 55 74AUP1Z125GN 55 74AUP1Z125GS 55 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram V CC R PU 3 6 X1 Y R bias 4 X2 1 EN 001aaf141 R = pull-up resistance. PU R = bias resistance. bias Fig 1. Logic symbol 74AUP1Z125 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 8 August 2012 2 of 32