74AUP2G240GD,125 NXP

74AUP2G240 Low-power dual inverting buffer/line driver 3-state Rev. 8 24 January 2013 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial Power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low-noise overshoot and undershoot < 10 % of V CC Input-disable feature allows floating input conditions I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP2G240 NXP Semiconductors Low-power dual inverting buffer/line driver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G240DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74AUP2G240GT 40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74AUP2G240GF 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 1 0.5 mm 74AUP2G240GD 40 Cto +125 C XSON8 plastic extremely thin small outline package no leads SOT996-2 8 terminals body 3 2 0.5 mm 74AUP2G240GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package no leads SOT902-2 8 terminals body 1.6 1.6 0.5 mm 74AUP2G240GN 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP2G240GS 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes 1 Type number Marking code 74AUP2G240DC p40 74AUP2G240GT p40 74AUP2G240GF p2 74AUP2G240GD p40 74AUP2G240GM p40 74AUP2G240GN p2 74AUP2G240GS p2 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74AUP2G240 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 24 January 2013 2 of 25