74AVC20T245 20-bit dual supply translating transceiver with configurable voltage translation 3-state Rev. 7 8 March 2012 Product data sheet 1. General description The 74AVC20T245 is a 20-bit, dual supply transceiver that enables bi-directional voltage level translation. The device can be used as two 10-bit transceivers or as a single 20-bit transceiver. It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output enable inputs (nOE), two direction inputs (nDIR) and dual supplies (V and V ). CC(A) CC(B) V and V can be independently supplied at any voltage between 0.8 V and 3.6 V CC(A) CC(B) making the device suitable for bi-directional voltage level translation between any of the low voltage nodes: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, nOE and nDIR are referenced to V , the 1Bn and 2Bn ports are referenced to V . A CC(A) CC(B) HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to assume a HIGH impedance OFF-state. The device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at CC(A) CC(B) GND level, all output ports will assume a high impedance OFF-state. 2. Features and benefits Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 2.5 V translation) 210 Mbit/s ( 1.1 V to 1.8 V translation) 74AVC20T245 NXP Semiconductors 20-bit dual supply translating transceiver 3-state 120 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC20T245DGG 40 C to +125 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mm 1 74AVC20T245DGV 40 C to +125 C TSSOP56 plastic thin shrink small outline package 56 leads SOT481-2 body width 4.4 mm 74AVC20T245BX 40 Cto+125 C HXQFN60 plastic compatible thermal enhanced extremely thin SOT1134-2 quad flat package no leads 60 terminals body 4 6 0.5 mm 1 Also known as TVSOP56. 4. Functional diagram 1DIR 2DIR 1OE 2OE 1A1 2A1 1B1 2B1 V V V V CC(A) CC(B) CC(A) CC(B) to other nine channels to other nine channels 001aal240 Fig 1. Logic diagram 74AVC20T245 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 8 March 2012 2 of 27