INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT173
Quad D-type flip-flop; positive-edge
trigger; 3-state
December 1990
Product specication
File under Integrated Circuits, IC06Philips Semiconductors Product specication
Quad D-type ip-op; positive-edge trigger; 3-state 74HC/HCT173
FEATURES synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both E inputs are HIGH one
n
Gated input enable for hold (do nothing) mode
set-up time prior to the LOW-to-HIGH clock transition, the
Gated output enable control
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
Edge-triggered D-type register
only one set-up time prior to the LOW-to-HIGH clock
Asynchronous master reset
transition.
Output capability: bus driver
The master reset input (MR) is an active HIGH
I category: MSI
CC
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
GENERAL DESCRIPTION
The 3-state output buffers are controlled by a 2-input NOR
The 74HC/HCT173 are high-speed Si-gate CMOS devices
gate. When both output enable inputs (OE and OE ) are
and are pin compatible with low power Schottky TTL
1 2
LOW, the data in the register is presented to the Q
(LSTTL). They are specified in compliance with JEDEC n
outputs. When one or both OE inputs are HIGH, the
standard no. 7A. n
outputs are forced to a high impedance OFF-state. The
The 74HC/HCT173 are 4-bit parallel load registers with
3-state output buffers are completely independent of the
clock enable control, 3-state buffered outputs (Q to Q )
0 3
register operation; the OE transition does not affect the
n
and master reset (MR).
clock and reset operations.
When the two data enable inputs (E and E ) are LOW, the
1 2
data on the D inputs is loaded into the register
n
QUICK REFERENCE DATA
GND = 0 V; T =25 C; t =t =6ns
amb r f
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
t / t propagation delay C = 15 pF; V =5V
PHL PLH L CC
CP to Q 17 17 ns
n
MR to Q 13 17 ns
n
f maximum clock frequency 88 88 MHz
max
C input capacitance 3.5 3.5 pF
I
C power dissipation notes 1 and 2 20 20 pF
PD
capacitance per ip-op
Notes
1. C is used to determine the dynamic power dissipation (P in W):
PD D
2 2
P =C V f + (C V f ) where:
D PD CC i L CC o
f = input frequency in MHz
i
f = output frequency in MHz
o
2
(C V f ) = sum of outputs
L CC o
C = output load capacitance in pF
L
V = supply voltage in V
CC
2. For HC the condition is V = GND to V
I CC
For HCT the condition is V = GND to V - 1.5 V
I CC
ORDERING INFORMATION
See 74HC/HCT/HCU/HCMOS Logic Package Information.
December 1990 2