74HC2G126GD,125 NXP

74HC2G126 74HCT2G126 Dual buffer/line driver 3-state Rev. 5 18 December 2013 Product data sheet 1. General description The 74HC2G126 74HCT2G126 is a dual buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide operating voltage from 2.0 V to 6.0 V Input levels: For 74HC2G126: CMOS level For 74HCT2G126: TTL level Complies with JEDEC standard no. 7A Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G126DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74HCT2G126DP 74HC2G126DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74HCT2G126DC 74HC2G126GD 40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT996-2 8 terminals body 3 2 0.5 mm 74HCT2G126GDNXP Semiconductors 74HC2G126 74HCT2G126 Dual buffer/line driver 3-state 4. Marking 1 Table 2. Marking codes Type number Marking code 74HC2G126DP H26 74HCT2G126DP T26 74HC2G126DC H26 74HCT2G126DC T26 74HC2G126GD H26 74HCT2G126GD T26 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1Y 1A 2 2 6 6 1 1OE 1 1 EN1 2Y A Y 2A 5 5 3 3 2OE 7 7 OE mna946 mna947 mna127 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one driver) 6. Pinning information 6.1 Pinning 74HC2G126 74HCT2G126 1OE 1 8 V CC 74HC2G126 74HCT2G126 1A 2 7 2OE 1OE 1 8 V CC 2Y 3 6 1Y 1A 2 7 2OE GND 4 5 2A 2Y 3 6 1Y GND 4 5 2A 001aak029 001aad984 Transparent top view Fig 4. Pin configuration SOT505-2 (TSSOP8) and Fig 5. Pin configuration SOT996-2 (XSON8) SOT765-1 (VSSOP8) 74HC HCT2G126 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 18 December 2013 2 of 15