74LV125PW,112 NXP

74LV125 Quad buffer/line driver 3-state Rev. 03 7 April 2009 Product data sheet 1. General description The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC125 and 74HCT125. The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. 2. Features n Wide operating voltage: 1.0 V to 5.5 V n Optimized for low voltage applications: 1.0 V to 3.6 V n Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC n Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb n Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV125N - 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74LV125D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV125DB - 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV125PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm74LV125 NXP Semiconductors Quad buffer/line driver 3-state 4. Functional diagram 2 1A 1Y 3 2 1 1 1OE 3 1 EN1 5 2A 2Y 6 5 6 2OE 4 4 3A 3Y 9 8 9 8 3OE 10 10 nY nA 12 4A 4Y 11 12 11 13 4OE 13 nOE mna229 mna227 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 5. Pinning information 5.1 Pinning 74LV125 1 14 1OE V CC 74LV125 1A 2 13 4OE 1OE 1 14 V 1Y 3 12 4A CC 1A 2 13 4OE 2OE 4 11 4Y 1Y 3 12 4A 2OE 4 11 4Y 2A 5 10 3OE 2A 5 10 3OE 6 9 2Y 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y 001aaj961 001aaj921 Fig 4. Pin conguration DIP14, SO14 Fig 5. Pin conguration SSOP14, TSSOP14 74LV125 3 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 7 April 2009 2 of 15