74LVC109D,112 NXP

74LVC109 Dual JK flip-flop with set and reset positive-edge trigger Rev. 5 29 November 2012 Product data sheet 1. General description The 74LVC109A is a dual positive edge triggered JK flip-flop featuring: individual J and K inputs clock (CP) inputs set (SD) and reset (RD) inputs complementary Q and Q outputs The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time before the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt trigger action in the clock input makes the circuit highly tolerant of slower clock rise and fall times. 2. Features and benefits 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C74LVC109 NXP Semiconductors Dual JK flip-flop with set and reset positive-edge trigger 3. Ordering information Table 1. Ordering information All types are specified from 40 C to +125 C. Type number Package Name Description Version 74LVC109D SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 74LVC109DB SSOP16 plastic shrink small outline package 16 leads body width 5.3 mm SOT338-1 74LVC109PW TSSOP16 plastic thin shrink small outline package 16 leads body width 4.4 mm SOT403-1 4. Functional diagram 511 1SD 2SD 5 11 SD S S 2 1J 1Q 6 J Q 2 14 14 2J 2Q 10 1J 1J 6 10 4 1CP CP 4 12 12 2CP C1 C1 FF 7 9 1Q 7 3 1K 3 13 Q K 1K 1K 13 9 2Q 2K RD 1 15 R R 1RD 2RD (a) (b) 115 mna858 mna856 Fig 1. Logic symbol Fig 2. IEC logic symbol Q C C C C K Q J C C C C S mna859 R C CP C Fig 3. Logic diagram for one flip-flop 74LVC109 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 29 November 2012 2 of 17