74LVC125A-Q100
Quad buffer/line driver with 5 V tolerant inputs/outputs;
3-state
Rev. 2 5 May 2020 Product data sheet
1. General description
The 74LVC125A-Q100 consists of four non-inverting buffers/line drivers with 3-state outputs (nY)
that are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume
a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to
the outputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 C to +85 C and from -40 C to +125 C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 2.3 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC125AD-Q100 -40 C to +125 C SO14 plastic small outline package; 14 leads; SOT108-1
body width 3.9 mm
74LVC125APW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
74LVC125ABQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1
enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 3 0.85 mmNexperia
74LVC125A-Q100
Quad buffer/line driver with 5 V tolerant inputs/outputs; 3-state
4. Functional diagram
2 1A 1Y 3
2
1
1 1OE
3
1
EN1
5 2A 2Y 6
5
4 2OE 6
4
9 3A 3Y 8
9
8
3OE
10
10
4A 4Y nA nY
12 11
12
11
4OE
13
13
nOE
mna228 mna229 mna227
Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram
5. Pinning information
5.1. Pinning
74LVC125A-Q100
terminal 1
index area
74LVC125A-Q100
1A 2 13 4OE
1Y 3 12 4A
1OE 1 14 V
CC
4 11
2OE 4Y
1A 2 13 4OE
2A 5 (1) 10 3OE
GND
1Y 3 12 4A
2Y 6 9 3A
2OE 4 11 4Y
5 10 aaa-006890
2A 3OE
Transparent top view
2Y 6 9 3A
(1) This is not a ground pin. There is no electrical or
GND 7 8 3Y
mechanical requirement to solder the pad. In case
aaa-006889
soldered, the solder land should remain floating or
connected to GND.
Fig. 4. Pin configuration for SOT108-1 (SO14) and
SOT402-1 (TSSOP14) Fig. 5. Pin configuration for SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol Pin Description
1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 data enable input (active LOW)
1A, 2A, 3A, 4A 2, 5, 9, 12 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V 14 supply voltage
CC
74LVC125A_Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 2 5 May 2020 2 / 13
GND 7 1 1OE
3Y 8 14 V
CC