74LVC16245AEV NXP

INTEGRATED CIRCUITS DATA SHEET 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state Product specication 2003 Nov 25 Supersedes data of 2003 Jan 30Philips Semiconductors Product specication 74LVC16245A; 16-bit bus transceiver with direction pin; 5 V tolerant; 74LVCH16245A 3-state FEATURES DESCRIPTION 5 V tolerant inputs/outputs for interfacing with 5 V logic The 74LVC(H)16245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most Wide supply voltage range from 1.2 to 3.6 V advanced CMOS compatible TTL families. Inputs can be CMOS low power consumption driven from either 3.3 or 5 V devices. In 3-state operation, TM MULTIBYTE flow-through standard pin-out outputs can handle 5 Volt. These features allow the use of architecture these devices as a mixed 3.3 and 5 V environment. Low inductance multiple power and ground pins for The 74LVC(H)16245A is a 16-bit transceiver featuring minimum noise and ground bounce non-inverting 3-state bus compatible outputs in both send Direct interface with TTL levels and receive directions. The device features two output enable (nOE) inputs for easy cascading and two High-impedance when V =0V CC send/receive (nDIR) inputs for direction control. nOE All data inputs have bushold (74LVCH16245A only) controls the outputs so that the buses are effectively Complies with JEDEC standard no. 8-1A isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver. ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V The 74LVCH16245A bushold data inputs eliminates the MM EIA/JESD22-A115-A exceeds 200 V. need for external pull-up resistors to hold unused inputs. QUICK REFERENCE DATA GND = 0 V; T =25 C; t =t 2.5 ns. amb r f SYMBOL PARAMETER CONDITIONS TYPICAL UNIT t /t propagation delay nAn to nBn; nBn to nAn C = 50 pF; V = 3.3 V 2.2 ns PHL PLH L CC C input capacitance 5.0 pF I C input/output capacitance 10 pF I/O C power dissipation capacitance per gate V = 3.3 V; notes 1 and 2 30 pF PD CC Notes 1. C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz; i f = output frequency in MHz; o C = output load capacitance in pF; L V = supply voltage in Volts; CC N = total load switching outputs; 2 (C V f ) = sum of the outputs. L CC o 2. The condition is V = GND to V . I CC 2003 Nov 25 2