74LVC2952A Octal registered transceiver with 5 V tolerant inputs/outputs 3-state Rev. 02 29 June 2004 Product data sheet 1. General description The 74LVC2952A is a high-performance, low power, low voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V and 5 V environment. The 74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit back-to-back registers store data owing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPAB, CPBA) provided that the clock enable (CEAB, CEBA) input is LOW. The data is then present at the 3-state output buffers, but is only accessible when the output enable (OEAB, OEBA) input is LOW. Data ow from A inputs to B outputs is the same as for B inputs to A outputs. 2. Features 5 V tolerant inputs/outputs for interfacing with 5 V logic Supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V Flow-through pin-out architecture Complies with JEDEC standard JESD8-B/JESD36 ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Specied from - 40 Cto+85 C and from - 40 C to +125 C.74LVC2952A Philips Semiconductors Octal registered transceiver 3. Quick reference data Table 1: Quick reference data GND = 0 V T = 25 C t = t 2.5 ns. amb r f Symbol Parameter Conditions Min Typ Max Unit t , t propagation delay C = 50 pF V = 3.3 V - 3.6 - ns PHL PLH L CC CPAB, CPBA to An, Bn f maximum clock frequency C = 50 pF V = 3.3 V - 250 - MHz max L CC C input capacitance - 5.0 - pF I C input/output capacitance - 10.0 - pF I/O 1 2 C power dissipation outputs enabled - 15.0 - pF PD capacitance per latch V = 3.3 V CC 1 C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in V CC N = total load switching outputs 2 (C V f ) = sum of the outputs. L CC o 2 The condition is V = GND to V . I CC 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74LVC2952AD - 40 C to +125 C SO24 plastic small outline package 24 leads body SOT137-1 width 7.5 mm 74LVC2952ADB - 40 C to +125 C SSOP24 plastic shrink small outline package 24 leads SOT340-1 body width 5.3 mm 74LVC2952APW - 40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 SOT355-1 leads body width 4.4 mm 9397 750 13251 Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 02 29 June 2004 2 of 19