74LVC4245APW NXP

74LVC4245A Octal dual supply translating transceiver 3-state Rev. 10 18 December 2012 Product data sheet 1. General description The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. The device features an output enable input (pin OE) for easy cascading and a send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the buses are effectively isolated. In suspend mode, when V is zero, there will be no current flow from one supply to the CC(A) other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be smaller than V (typical 0.7 V). diode V V , except in suspend mode. CC(A) CC(B) 2. Features and benefits 5 V tolerant inputs/outputs, for interfacing with 5 V logic Wide supply voltage range: 3 V bus (V ): 1.5 V to 3.6 V CC(B) 5 V bus (V ): 1.5 V to 5.5 V CC(A) CMOS low-power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedance when V = 0 V CC(A) Complies with JEDEC standard no. JESD8B/JESD36 ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C74LVC4245A NXP Semiconductors Octal dual supply translating transceiver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC4245AD 40 C to +125 C SO24 plastic small outline package 24 leads SOT137-1 body width 7.5 mm 74LVC4245ADB 40 C to +125 C SSOP24 plastic shrink small outline package 24 leads SOT340-1 body width 5.3 mm 74LVC4245APW 40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74LVC4245ABQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced SOT815-1 very thin quad flat package no leads 24 terminals body 3.5 5.5 0.85 mm 4. Functional diagram DIR 2 OE 22 A0 3 B0 21 A1 4 22 B1 G3 20 3EN1 A2 2 5 3EN2 B2 19 A3 1 6 B3 3 21 2 18 A4 7 4 20 B4 17 5 19 A5 8 6 18 B5 16 7 17 A6 9 B6 8 16 15 A7 9 15 10 B7 10 14 14 mna452 mna453 Fig 1. IEC Logic symbol Fig 2. Logic diagram 74LVC4245A All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 10 18 December 2012 2 of 18