74LVCH16244AEVG,5 NXP

74LVC16244A 74LVCH16244A 16-bit buffer/line driver 5 V input/output tolerant 3-state Rev. 16 21 September 2021 Product data sheet 1. General description The 74LVC16244A 74LVCH16244A is a 16-bit buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The OFF I circuitry disables the output, preventing the potentially damaging backflow current through the OFF device when it is powered down. The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V 5 V tolerant inputs/outputs for interfacing with 5 V logic I circuitry provides partial Power-down mode operation OFF CMOS low power consumption Multibyte flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels High-impedance when V = 0 V CC All data inputs have bus hold. (74LVCH16244A only) Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC16244A 74LVCH16244A 16-bit buffer/line driver 5 V input/output tolerant 3-state 3. Ordering information Table 1. Ordering information Type number Temperature range Package Name Description Version 74LVC16244ADGG -40 C to +125 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mm 74LVCH16244ADGG 74LVC16244ADGV -40 C to +125 C TVSOP48 plastic thin shrink small outline SOT480-1 package 48 leads body width 4.4 mm 74LVCH16244ADGV lead pitch 0.4 mm 4. Functional diagram 47 2 36 13 1A0 1Y0 3A0 3Y0 46 3 35 14 1A1 1Y1 3A1 3Y1 1 1OE EN1 48 2OE EN2 44 5 33 16 25 1A2 3A2 1Y2 3Y2 3OE EN3 24 4OE EN4 6 17 43 32 47 2 1A3 1Y3 3A3 3Y3 1A0 1 1 1Y0 46 3 1A1 1Y1 1 25 44 5 1OE 3OE 1A2 1Y2 43 6 1A3 1Y3 41 8 2A0 1 2 2Y0 40 9 41 8 30 19 2A1 2Y1 2A0 2Y0 4A0 4Y0 38 11 2A2 2Y2 37 12 2A3 2Y3 40 9 29 20 36 13 2A1 4A1 2Y1 4Y1 3A0 1 3 3Y0 35 14 3A1 3Y1 33 16 11 22 3A2 3Y2 38 27 17 2A2 2Y2 4A2 4Y2 32 3A3 3Y3 30 19 4A0 1 4 4Y0 29 20 37 12 26 23 4A1 4Y1 2A3 2Y3 4A3 4Y3 27 22 4A2 4Y2 26 23 48 24 4A3 4Y3 2OE 4OE mna996 001aae231 Fig. 1. Logic symbol Fig. 2. IEC logic symbol V CC data input to internal circuit mna705 Fig. 3. Bus hold circuit 74LVC LVCH16244A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 16 21 September 2021 2 / 13