CBTU4411EE,518 NXP

CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 ON resistance Rev. 4 18 June 2012 Product data sheet 1. General description This 11-bit bus switch is designed for 1.7 V to 1.9 V V operation and SSTL 18 select DD input levels. Each Host port pin (HPn) is multiplexed to one of four DIMM port pins (xDPn). The selection of the DIMM port to be connected to the Host port is controlled by a decoder driven by three hardware select pins S0, S1 and EN. Driving pin EN HIGH disconnects all DIMM ports from their respective host ports. When EN is driven LOW, pins S0 and S1 select one of four DIMM ports to be connected to their respective host port. When disconnected, any DIMM port is terminated to the externally supplied voltage V by bias means of an on-chip pull-down resistor of typically 400 . The ON-state connects the Host port to the DIMM port through a 12 nominal series resistance. The design is intended to have only one DIMM port active at any time. The CBTU4411 can also be configured to support a differential strobe signal on channel 10 (TRUE) and channel 9 (complementary Strobe). When its LVCMOS 3 configuration input strobe enable (STREN) is HIGH, channel 10 is pulled up to of V 4 DD internally by a resistive divider when the DIMM port is idle. When the CBTU4411 is disabled (EN = HIGH in Strobe mode), the pull-down on channel 10 is disabled for current savings, pulling channel 10 to V . When strobe enable (STREN) is LOW, channel 10 DD behaves the same as all other channels. The select inputs (S0, S1) are pseudo-differential type SSTL 18. A reference voltage should be provided to input pin VREF at nominally 0.5V . This topology provides DD accurate control of switching times by reducing dependency on select signal slew rates. S0 and S1 are provided with selectable input termination to 0.5V (active when LVCMOS DD input TERM is HIGH). When the CBTU4411 is disabled (EN = HIGH), both S0 and S1 inputs are pulled LOW. The part incorporates a very low crosstalk design. It has a very low skew between outputs (< 30 ps) and low skew (< 30 ps) for rising and falling edges. The part has optimal performance in DDR2 data bus applications. Each switch has been optimized for connection to 1- or 2-rank DIMMs. The low internal RC time constant of the switch allows data transfer to be made with minimal propagation delay. The CBTU4411 is characterized for operation from 0 C to +85 C.CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 ON resistance 2. Features and benefits Enable (EN) and select signals (S0, S1) are SSTL 18 compatible Optimized for use in Double Data Rate 2 (DDR2) SDRAM applications Suitable to be used with 400 Mbit/s to 800 Mbit/s, 200 MHz to 400 MHz DDR2 data bus Switch ON-resistance is designed to eliminate the need for series resistor to DDR2 SDRAM 12 ON-resistance Controlled enable/disable times support fast bus turnaround Pseudo-differential select inputs support accurate and low-skew control of switching times Selectable built-in termination resistors on the Sn inputs Internal 400 pull-down resistors on xDPn port VBIAS input for optimal DIMM-port pull-down when disabled 3 Configurable to support differential strobe with pull-up to of V on channel 10 4 DD when idle Low differential skew Matched rise/fall slew rate Low crosstalk data-data/data-DQM Simplified 1 : 4 switch position control by 2-bit encoded input Single input pin puts all bus switches in OFF (high-impedance) position Latch-up protection exceeds 500 mA per JESD78 ESD protection exceeds 1500 V HBM per JESD22-A114 and 750 V CDM per JESD22-C101 3. Ordering information Table 1. Ordering information T =0 C to +85 C. amb Type number Package Name Description Version CBTU4411EE LFBGA72 plastic low profile fine-pitch ball grid array package SOT856-1 72 balls body 7 7 1.05 mm CBTU4411 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 18 June 2012 2 of 21