CBTV24DD12
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2
applications
Rev. 3.2 19 April 2016 Product data sheet
1. General description
CBTV24DD12 is designed for 1.8 V/2.5 V/3.3 V supply voltage operation and it supports
Pseudo Open Drain (POD), SSTL_12, SSTL_15 or SSTL_18 signaling and CMOS select
input levels. This device is designed for operation in DDR4, DDR3 or DDR2 memory bus
systems, with speeds up to 3200 MT/s.
The CBTV24DD12 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 12-bit wide
bus. Each 12-bit wide A-port can be switched to one of two ports B and C, for all bits
simultaneously. Each port is non-directional due to the use of FET switches, allowing a
multitude of applications requiring high-bandwidth switching or multiplexing.
The selection of the port is by a simple CMOS input (SELect). Another CMOS input
(ENable) is available to allow all ports to be disconnected. The SEL0, SEL1 and EN input
signals are designed to operate transparently as CMOS input level signals up to 3.3 V.
CBTV24DD12 uses NXPs proprietary high-speed switch architecture providing high
bandwidth, very little insertion loss, return loss, and very low propagation delay, allowing
use in many applications requiring switching or multiplexing of high-speed signals. It is
available in a 3.0 mm 8.0 mm TFBGA48 package with 0.65 mm ball pitch, for optimal
size versus board layout density considerations. It is characterized for operation from
10 C to +85 C.
2. Features and benefits
2.1 Topology
12-bit bus width
1 : 2 switch/MUX topology
Bidirectional operation
Simple CMOS select pins (SEL0, SEL1)
Simple CMOS enable pin (EN)
2.2 Performance
3200 MT/s throughput
7.4 GHz bandwidth (for both single-ended and differential signals)
Low ON insertion loss
Low return loss
Low crosstalk
High OFF isolationCBTV24DD12
NXP Semiconductors
12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications
POD_12, SSTL_12, SSTL_15 or SSTL_18 signaling
Low R (8 typical)
ON
Low R (<1 )
ON
2.3 General attributes
1.8 V/2.5 V/3.3 V supply voltage operation
Very low supply current (600 A typical)
Back current protection on all the I/O pins of these switches
ESD robustness exceeds 2.5 kV HBM, 1 kV CDM
Available in TFBGA48 package, 3.0 mm 8.0 mm 1 mm size, 0.65 mm pitch,
Pb-free/Dark Green
3. Applications
DDR4/DDR3/DDR2 memory bus systems
NVDIMM module
Systems requiring high-speed multiplexing
Flash memory array subsystem
4. Ordering information
Table 1. Ordering information
Type number Topside Package
mark
Name Description Version
CBTV24DD12ET V2412 TFBGA48 plastic low profile fine-pitch ball grid array package; 48 SOT1365-1
balls; body 3 8 1 mm; 0.65 mm pitch
4.1 Ordering options
Table 2. Ordering options
Type number Orderable Package Packing method Minimum Temperature
part number order
quantity
CBTV24DD12ET CBTV24DD12ETY TFBGA48 Reel 13 Q1/T1 4500 T = 10 C to +85 C
amb
*Standard mark SMD dry pack
CBTV24DD12 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.2 19 April 2016 2 of 19