Address Control Data DSP56301 Freescale Semiconductor Rev. 10, 7/2006 Technical Data DSP56301 24-Bit Digital Signal Processor 52 6 6 3 Memory Expansion Area The DSP56301 is intended X Data Y Data for general-purpose digital Program Host Triple ESSI SCI RAM RAM RAM Interface signal processing, Timer 2048 24 2048 24 4096 24 bits bits bits particularly in multimedia (Default) (Default) (Default) and telecommunication Peripheral applications, such as video Expansion Area 24 conferencing and cellular External Address XAB Address telephony. Generator PAB Bus Unit Switch DAB Six-Channel 14 DMA Unit External Bus 24-Bit Interface Boot- DSP56300 and strap I-Cache Core ROM Control DDB 24 YDB External Internal XDB Data Whats New Data PDB Bus Bus Rev. 10 includes the following Switch GDB changes: Removes all references to Power EXTAL Management Motorola. No specifications or Clock Data ALU Program Program Program 6 part numbers were changed. + 24 24 56 56-bit MAC XTAL JTAG Interrupt Decode Address Two 56-bit Accumulators PLL Controller Controller Generator OnCE 56-bit Barrel Shifter MODD/IRQD 2 MODC/IRQC RESET MODB/IRQB PINIT/NMI MODA/IRQA Figure 1. DSP56301 Block Diagram The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high-performance, single clock cycle per instruction engine. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.03.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products. Freescale Semiconductor, Inc., 1996, 2006. All rights reserved. YABTable of Contents DSP56301 Features.............................................................................................................................................iii Target Applications.............................................................................................................................................iv Product Documentation ......................................................................................................................................iv Chapter 1 Signals/Connections 1.1 Power ................................................................................................................................................................1-4 1.2 Ground ..............................................................................................................................................................1-4 1.3 Clock.................................................................................................................................................................1-5 1.4 Phase Lock Loop (PLL)....................................................................................................................................1-5 1.5 External Memory Expansion Port (Port A) ......................................................................................................1-6 1.6 Interrupt and Mode Control ..............................................................................................................................1-9 1.7 Host Interface (HI32)......................................................................................................................................1-10 1.8 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-16 1.9 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-18 1.10 Serial Communication Interface (SCI) ...........................................................................................................1-19 1.11 Timers .............................................................................................................................................................1-20 1.12 JTAG/OnCE Interface.....................................................................................................................................1-21 Chapter 2 Specifications 2.1 Maximum Ratings.............................................................................................................................................2-1 2.2 Absolute Maximum Ratings .............................................................................................................................2-2 2.3 Thermal Characteristics ....................................................................................................................................2-2 2.4 DC Electrical Characteristics............................................................................................................................2-2 2.5 AC Electrical Characteristics............................................................................................................................2-4 Chapter 3 Packaging 3.1 TQFP Package Description...............................................................................................................................3-2 3.2 TQFP Package Mechanical Drawing..............................................................................................................3-11 3.3 MAP-BGA Package Description....................................................................................................................3-12 3.4 MAP-BGA Package Mechanical Drawing.....................................................................................................3-23 Chapter 4 Design Considerations 4.1 Thermal Design Considerations........................................................................................................................4-1 4.2 Electrical Design Considerations......................................................................................................................4-2 4.3 Power Consumption Considerations.................................................................................................................4-3 4.4 PLL Performance Issues ...................................................................................................................................4-4 4.5 Input (EXTAL) Jitter Requirements .................................................................................................................4-4 Chapter A Power Consumption Benchmark Index Data Sheet Conventions OVERBAR Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN V /V True Asserted IL OL PIN V /V False Deasserted IH OH PIN V /V True Asserted IH OH PIN V /V False Deasserted IL OL Note: Values for V , V , V , and V are defined by individual product specifications. IL OL IH OH DSP56301 Technical Data, Rev. 10 ii Freescale Semiconductor