DSP56371 Freescale Semiconductor Rev. 4.1, 1/2007 Data Sheet: Technical Data DSP56371 Data Sheet Table of Contents 1Introduction 1 Introduction 1 2 DSP56371 Overview . 1 The DSP56371 is a high density CMOS device with 3 Signal/Connection Descriptions . 10 5.0-V compatible inputs and outputs. 4 Maximum Ratings 33 5 Power Requirements . 34 NOTE 6 Thermal Characteristics . 35 This document contains information on a 7 DC Electrical Characteristics . 36 8 AC Electrical Characteristics 37 new product. Specifications and 9 Internal Clocks 37 information herein are subject to change 10 External Clock Operation 38 without notice. 11 Reset, Stop, Mode Select, and Interrupt Timing . 39 12 Serial Host Interface SPI Protocol Timing 42 Finalized specifications may be published after further 2 13 Serial Host Interface (SHI) I C Protocol Timing . 47 characterization and device qualifications are completed. 14 Enhanced Serial Audio Interface Timing . 49 15 Digital Audio Transmitter Timing . 54 For software or simulation models (for example, IBIS 16 Timer Timing 55 files), contact sales or go to www.freescale.com. 17 GPIO Timing 55 18 JTAG Timing 56 19 Package Information 58 20 Design Considerations 64 2 DSP56371 Overview 21 Electrical Design Considerations 65 22 Power Consumption Benchmark 67 2.1 Introduction This manual describes the DSP56371 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules. The DSP56371 is a member of Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved.DSP56371 Overview the DSP56300 family of programmable CMOS DSPs. The DSP56371 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. Changes in core functionality specific to the DSP56371 are also described in this manual. See Figure 1. for the block diagram of the DSP56371. 2 12 12 11 5 Memory Expansion Area SHI Triple ESAI ESAI 1 GPIO EFCOP X Data Y Data Program Interface Timer Interface Interface RAM RAM RAM 36K 24 48K 24 4K 24 ROM ROM ROM 2 64K 24 32K 24 32K 24 DAX Peripheral Expansion Area YAB Address XAB Generation Unit PAB DAB Six Channel DMA Unit 24-Bit Bootstrap DSP56300 ROM Core DDB Internal YDB Data XDB Bus PDB Switch GDB Power Mgmt. Clock 4 Data ALU Program Program Program Gen- JTAG PLL Interrupt Decode Address + 24 24 56 56-bit MAC erator OnCE Controller Controller Generator Two 56-bit Accumulators 56-bit Barrel Shifter MODA/IRQA EXTAL MODB/IRQB RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1. DSP56371 Block Diagram 2.2 DSP56300 Core Description The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Motorola s popular DSP56000 core family while retaining code compatibility with it. DSP56371 Data Sheet, Rev. 4.1 2 Freescale Semiconductor PIO EB PM EB XM EB YM EB