GTL2014PW,112 NXP

GTL2014 4-bit LVTTL to GTL transceiver Rev. 3.1 16 August 2021 Product data sheet 1 General description The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface with a GTL-/GTL/GTL+ bus, where GTL-/GTL/GTL+ refers to the reference voltage of the GTL bus and the input/output voltage thresholds associated with it. The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or as a LVTTL to GTL interface. The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or 5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant. The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage open-drain output applications. GTL2014 is pin-to-pin backward compatible to the GTL2005 (labels for A port and B port are interchanged). GTL2014s V tracks down to 0.5 V for low voltage CPU, propagation ref delays are slightly longer, while GTL2005s V linearity degrades below 0.8 V and has ref shorter propagation delay. fast t PD GTL2005 GTL2014 slow t PD GTL GTL- GTL+ 002aab378 Figure 1.GTL2005/GTL2014 positioning 2 Features and benefits Operates as a 4-bit GTL-/GTL/GTL+ sampling receiver or as a LVTTL to GTL-/GTL/ GTL+ driver 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input GTL input and output 3.6 V tolerant V adjustable from 0.5 V to V /2 ref CC Partial power-down permitted ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101 Latch-up protection exceeds 500 mA per JESD78 Package offered: TSSOP14NXP Semiconductors GTL2014 4-bit LVTTL to GTL transceiver 3 Quick reference data Table 1.Quick reference data T = 25 C amb Symbol Parameter Conditions Min Typ Max Unit t LOW to HIGH propagation delay An-to-Bn C = 50 pF V = 3.3 V - 2.8 - ns PLH L CC t HIGH to LOW propagation delay An-to-Bn C = 50 pF V = 3.3 V - 3.4 - ns PHL L CC t LOW to HIGH propagation delay Bn-to-An C = 50 pF V = 3.3 V - 5.2 - ns PLH L CC t HIGH to LOW propagation delay Bn-to-An C = 50 pF V = 3.3 V - 4.9 - ns PHL L CC C input capacitance control inputs V = 3.0 V or 0 V - 2 2.5 pF i I C input/output capacitance A port V = 3.0 V or 0 V - 4.6 6 pF io O B port V = V or 0 V - 3.4 4.3 pF O TT 4 Ordering information Table 2.Ordering information Type number Topside Package mark Name Description Version GTL2014PW GTL2014 SOT402-1 TSSOP14 plastic thin shrink small outline package 10 leads body width 4.4 mm Standard packing quantities and other packaging data are available at www.nxp.com/ packages/. 4.1 Ordering options Table 3.Ordering options Type number Orderable part Package Packing method Minimum Temperature number order quantity 1 GTL2014PW GTL2014PW, 118 TSSOP14 REEL 13 Q1/T1 2500 T = -40 C to +85 C amb *STANDARD MARK GTL2014PWZ TSSOP14 GTL2014PW REEL 13 Q1/T1 2500 T = -40 C to +85 C amb *STANDARD MARK 2 SSB 1 Discontinued in 202108008DN - drop in replacement is GTL2014PWZ - this is documented in PCN:202102035F01. 2 This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses. GTL2014 All information provided in this document is subject to legal disclaimers. NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.1 16 August 2021 2 / 18