GTL2034PW,118 NXP

GTL2034 4-bit GTL to GTL buffer Rev. 1.1 20 December 2021 Product data sheet 1 General description The GTL2034 is a 4-bit GTL-/GTL/GTL+ bus buffer. The GTL2034 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage open-drain output applications. 2 Features Operates as a 4-bit GTL-/GTL/GTL+ to GTL-/GTL/GTL+ bus buffer 3.0 V to 3.6 V operation GTL input and output 3.6 V tolerant V adjustable from 0.5 V to V / 2 ref CC Partial power-down permitted ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101 Latch-up protection exceeds 500 mA per JESD78 Package offered: TSSOP14 3 Quick reference data Table 1.Quick reference data T = 25 C amb Symbol Parameter Conditions Min Typ Max Unit t LOW-to-HIGH propagation delay GTL BIn to BOn C = - 3.1 8 ns PLH L 50 pF V = 3.3 V CC t HIGH-to-LOW propagation delay - 4.1 10 ns PHL C input capacitance GTL outputs disabled - 4.5 - pF i V = 0 V or 3.0 V I/O 4 Ordering information Table 2.Ordering information Type number Topside Package marking Name Description Version GTL2034PW GTL2034 TSSOP14 plastic thin shrink small outline package 14 leads body width 4.4 SOT402-1 mmNXP Semiconductors GTL2034 4-bit GTL to GTL buffer 4.1 Ordering options Table 3.Ordering options 1 Type number Orderable part Package Packing method Minimum order Temperature number quantity 2 GTL2034PW GTL2034PW,118 TSSOP14 REEL 13 Q1/T1 NDP 2500 T = -40 C to +85 C amb GTL2034PWZ TSSOP14 REEL 13 Q1/T1 NDP SSB 2500 T = -40 C to +85 C amb 3 1 Standard packing quantities and other packaging data are available at www.nxp.com/packages/. 2 Discontinued in 202111031DN drop in replacement is GTL2034PWZ 3 This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses. 5 Functional diagram GTL2034 BI0 BO0 BI1 BO1 BI2 BO2 BI3 BO3 VREF 002aab148 Figure 1.Logic diagram of GTL2034 6 Pinning information 6.1 Pinning 1 14 n.c. V CC 2 13 BO0 BI0 BO1 3 12 BI1 4 11 VREF GTL2034PW GND 5 10 BO2 BI2 BO3 6 9 BI3 7 GND 8 GND 002aab147 Figure 2.Pin configuration for TSSOP14 GTL2034 All information provided in this document is subject to legal disclaimers. NXP B.V. 2021. All rights reserved. Product data sheet Rev. 1.1 20 December 2021 2 / 14