HEF40240BP NXP

HEF40240B Octal inverting buffers with 3-state outputs Rev. 5 15 November 2011 Product data sheet 1. General description The HEF40240B is an octal inverting buffer with 3-state outputs. It features output stages with high current output capability suitable for driving highly capacitive loads. The 3-state outputs are controlled by the output enable inputs nOE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. The device also features hysteresis on all inputs to improve noise immunity. Schmitt-trigger action makes the inputs highly tolerant to slow input rise and fall times. The HEF40240B is pin and functionally compatible with the TTL 240 device. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Tolerant of slow input rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF40240BP DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 HEF40240BT SO20 plastic small outline package 20 leads body width 7.5 mm SOT163-1HEF40240B NXP Semiconductors Octal inverting buffers with 3-state outputs 4. Functional diagram 2 18 1A0 1Y0 4 16 1A1 1Y1 6 14 1A2 1Y2 8 12 1A3 1Y3 1 1OE 11 9 nA0 nY0 2A0 2Y0 13 7 nA1 nY1 2A1 2Y1 15 5 2A2 2Y2 nA2 nY2 17 3 2A3 2Y3 nA3 nY3 19 2OE nOE 001aal325 001aal373 Fig 1. Functional diagram Fig 2. Logic diagram 5. Pinning information 5.1 Pinning HEF40240B 1OE 1 20 V DD 1A0 2 19 2OE HEF40240B 2Y3 3 18 1Y0 1 20 1OE V DD 1A1 4 17 2A3 2 19 1A0 2OE 5 16 2Y2 1Y1 3 18 2Y3 1Y0 4 17 1A2 6 15 2A2 1A1 2A3 5 2Y2 16 1Y1 2Y1 7 14 1Y2 6 1A2 15 2A2 1A3 8 13 2A1 2Y1 7 14 1Y2 1A3 8 13 2A1 2Y0 9 12 1Y3 2Y0 9 12 1Y3 10 11 V 2A0 SS V 10 11 2A0 SS 001aal326 001aal372 Fig 3. Pin configuration DIP20 Fig 4. Pin configuration SO20 HEF40240B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 15 November 2011 2 of 15