HEF4517B
Dual 64-bit static shift register
Rev. 7 11 November 2011 Product data sheet
1. General description
The HEF4517B consists of two identical, independent 64-bit static shift registers. Each
register has separate clock (nCP), data input (nD), parallel input-enable/output-enable
(nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to
nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of
the clock, regardless of the state of nPE/OE.
When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode.
When nPE/OE is HIGH, the outputs are disabled (high-impedance OFF-state), the 64-bit
shift register is divided into four 16-bit shift registers with nD, nQ16, nQ32 and nQ48 as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the
clock input makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended V power supply range of 3 V to 15 V referenced to V
DD SS
(usually ground). Unused inputs must be connected to V , V , or another input.
DD SS
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C
Type number Package
Name Description Version
HEF4517BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4517BT SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1HEF4517B
NXP Semiconductors
Dual 64-bit static shift register
4. Functional diagram
1D
7
1CP 64-BIT STATIC SHIFT REGISTER
4
1PE/OE
3 INPUT/3-STATE-OUTPUT CIRCUITRY
1Q64
5
1Q48
2
1Q32
6
1Q16
1
2D
9
2CP 64-BIT STATIC SHIFT REGISTER
12
2PE/OE
13 INPUT/3-STATE-OUTPUT CIRCUITRY
2Q64
11
2Q48
14
2Q32
10
2Q16
15
001aae694
Fig 1. Functional diagram
HEF4517B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 11 November 2011 2 of 16