TC74HC4020AP(F) Toshiba

TC74HC4020,4040AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC4020AP, TC74HC4020AF TC74HC4040AP, TC74HC4040AF TC74HC4020AP/AF 14-Stage Binary Counter TC74HC4040AP/AF 12-Stage Binary Counter TC74HC4020AP, TC74HC4040AP The TC74HC4020A/TC74HC4040A are high speed CMOS BINARY COUNTER/DIVIDERs fabricated with silicon gate 2 C MOS technology. They achieve the high speed operetion similar to equivalent LSTTL while maintaining the CMOS dissipation. The TC74HC4020A is a 14-STAGE BINARY COUNTER, and the TC74HC4040A is a 12-STAGE BINARY COUNTER. Setting CLR to high resets the counter to low. TC74HC4020AF, TC74HC4040AF A negative transition on the CK input brings one increment into the counter. The TC74HC4020A provides 12 divided outputs: 1st stage and stage 4 thru stage 14. At Q14, a 1/16384 divided frequency will be output. The TC74HC4040A provides all divided output stages, and at Q12, a 1/4096 divided frequency will be output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Weight Features DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) High speed: f = 73 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 4020B/4040B Start of commercial production 1988-05 1 2014-03-01 TC74HC4020,4040AP/AF Pin Assignment TC74HC4020A TC74HC4040A IEC Logic Symbol TC74HC4020A TC74HC4040A Truth Table CK CLR Output State X H All Output = L L No Change L Adovance to Next State X: Dont care 2 2014-03-01