MC9RS08KA8CTG NXP

Freescale Semiconductor Document Number: MC9RS08KA8 Rev. 4, 6/2009 Data Sheet: Technical Data MC9RS08KA8 20-Pin W-SOIC 16-Pin W-SOIC Case 751D Case 751G TBD TBD MC9RS08KA8 Series 20-Pin PDIP 16-Pin PDIP Case 738C Case 648 Covers: MC9RS08KA8 TBD TBD MC9RS08KA4 16-Pin TSSOP Features: Case 948F 8-Bit RS08 Central Processor Unit (CPU) Up to 20 MHz CPU at 1.8 V to 5.5 V across temperature Single-Wire background debug interface range of 40C to 85C Breakpoint capability to allow single breakpoint setting Subset of HC08 instruction set with added BGND during in-circuit debugging instruction Peripherals On-Chip Memory ADC 12-channel, 10-bit resolution 2.5 s 8 KB flash read/program/erase over full operating conversion time automatic compare function operation voltage and temperature KA4 has 4 KB flash in stop fully functional from 2.7 V to 5.5 V (8-channels 254 byte random-access memory (RAM) KA4 has 126 available on 16-pin package) byte RAM TPM One 2-channel selectable input capture, output Security circuitry to prevent unauthorized access to compare, or buffered edge- or center-aligned PWM on RAM and flash contents each channel Power-Saving Modes IIC Inter-Integrated circuit bus module capable of Wait and stop operation up to 100 kbps with maximum bus loading Wakeup from power-saving modes using real-time capable of higher baudrates with reduced loading interrupt (RTI), KBI, or ACMP MTIM1 and MTIM2 Two 8-bit modulo timers Clock Source Options KBI Keyboard interrupts with rising or falling edge Oscillator (XOSC) Loop-Control Pierce oscillator detect eight KBI ports in 16-pin and 20-pin packages crystal or ceramic resonator range of 31.25 kHz to ACMP Analog comparator: full rail-to-rail supply 39.0625 kHz or 1 MHz to 5 MHz operation option to compare to fixed internal bandgap Internal Clock Source (ICS) Internal clock source reference voltage can operate in stop mode module containing a frequency-locked-loop (FLL) Input/Output controlled by internal or external reference precision 14/18 GPIOs including one output only pin and one trimming of internal reference allows 0.2% resolution input only pin and 2% deviation over temperature and voltage Hysteresis and configurable pullup device on all input supports bus frequencies up to 10 MHz pins configurable slew rate and drive strength on all System Protection output pins Watchdog computer operating properly (COP) reset Package Options with option to run from dedicated 1 kHz internal clock 16-pin SOIC, PDIP or TSSOP source or bus clock 20-pin SOIC or PDIP Low-Voltage detection with reset or interrupt Illegal opcode detection with reset Illegal address detection with reset Flash block protection Development Support This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2008-2009. All rights reserved.Table of Contents 1 MCU Block Diagram .3 3.9 AC Characteristics 18 2 Pin Assignments 3 3.9.1 Control Timing . 19 3 Electrical Characteristics .5 3.9.2 TPM/MTIM Module Timing 20 3.1 Introduction .5 3.10 Analog Comparator (ACMP) Electrical 20 3.2 Parameter Classification .5 3.11 Internal Clock Source Characteristics . 21 3.3 Absolute Maximum Ratings 6 3.12 ADC Characteristics 21 3.4 Thermal Characteristics .6 3.13 Flash Specifications . 23 3.5 ESD Protection and Latch-Up Immunity .7 4 Ordering Information . 26 3.6 DC Characteristics .8 5 Mechanical Drawings 26 3.7 Supply Current Characteristics .15 3.8 External Oscillator (XOSC) Characteristics .18 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: