Document Number: MC9S08DZ128 Freescale Semiconductor, Inc. Rev. 2, 07/2015 Data Sheet MC9S08DZ128 Series Data Sheet with Addenda Rev.2 of the MC9S08DZ128 Series Data Sheet has three parts: The revision 2 of the addendum to revision 1 of the data sheet, immediately following this cover page. The revision 1 of the addendum to revision 1 of the data sheet, following the revision 2 of the addendum. Revision 1 of the data sheet, following the addendum revision 1. The changes described in the addenda have not been implemented in the specified pages. 2008-2015 Freescale Semiconductor, Inc. All rights reserved.Freescale Semiconductor, Inc. Document Number: MC9S08DZ128AD Data Sheet Addendum Rev. 2, 07/2015 Addendum Rev.2 to Rev. 1 of the MC9S08DZ128 Series Data Sheet This addendum identifies changes to Rev. 1 of the MC9S08DZ128 Series Data Sheet. The changes described in this addendum have not been implemented in the specified pages. 1 MCG Control Register 3 Field Descriptions Location: Table 8-7, Page 176 The last sentence of bit 4 (DIV32) description should be changed fromWrites to this bit are ignored if PLLS bit is set toDIV32 must be cleared when the PLL is selected The correct description should be: Field Description 4 Divide-by-32 Enable Controls an additional divide-by-32 factor to the external reference clock for the FLL DIV32 when RANGE bit is set. When the RANGE bit is 0, this bit has no effect. DIV32 must be cleared when the PLL is selected. 0 Divide-by-32 is disabled. 1 Divide-by-32 is enabled when RANGE=1. 2 Initializing the MCG Location: Section 8.5.1.1, Page 186 The last sentence in the note after step 6 should be removed. The note should be 2008-2015 Freescale Semiconductor, Inc. All rights reserved.