Freescale SemiconductorFreescale Semiconductor Document Number: MC9S08GW64 Rev. 3, 1/2011 Data Sheet: Data Sheet: Technical Data 64-LQFP 80-LQFP MC9S08GW64 Series Case 840F MC9S08GW64Case 917A 10 10 14 14 Covers: MC9S08GW64 and MC9S08GW32 comparator can be used as hardware breakpoint. Full mode, Comparator A compares address and Comparator B compares data. 8-Bit HCS08 Central Processor Unit (CPU) Supports both tag and force breakpoints Peripherals New version of S08 core with same performace as traditional S08 and lower power LCD up to 440 or 836 LCD driver with internal charge pump and Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 3.6 V option to provide an internally regulated LCD reference that can be to 1.8 V, across temperature range of 40 C to 85 C trimmed for contrast control HC08 instruction set with added BGND instruction ADC16 two analog-to-digital converters 16-bit resolution one Support for up to 48 interrupt/reset sources dedicated differential per ADC up to 16-ch up to 2.5 s conversion On-Chip Memory time for 12-bit mode automatic compare function hardware averaging calibration registers temperature sensor internal bandgap Flash read/program/erase over full operating voltage and temperature reference channel operation in stop3 fully functional from 3.6 V to Random-access memory (RAM) 1.8 V Security circuitry to prevent unauthorized access to RAM and flash PRACMP three rail to rail programmable reference analog contents comparator up to 8 inputs on-chip programmable reference generator Power-Saving Modes output selectable interrupt on rising, falling, or either edge of comparator output operation in stop3 Two low power stop modes and reduced power wait mode SCI four full duplex non-return to zero (NRZ) LIN master extended Low power run and wait modes allow peripherals to run while voltage break generation LIN slave extended break detection wakeup on regulator is in standby active edge SCI0 designed for AMR operation TxD of SCI1 and SCI2 Peripheral clock gating register can disable clocks to unused modules, can be modulated with timers and RxD can recieved through thereby reducing currents PRACMP Very low power external oscillator that can be used in stop2 or stop3 SPI three full-duplex or single-wire bidirectional double-buffered modes to provide accurate clock source to real time counter transmit and receive master or slave mode MSB-first or LSB-first 6 s typical wakeup time from stop3 mode shifting SPI0 designed for AMR opeartion IIC up to 100 kbps with maximum bus loading multi-master Clock Source Options operation programmable slave address interrupt driven byte-by-byte data transfer supporting broadcast mode and 10-bit addressing Oscillator (XOSC1) Loop-control Pierce oscillator Crystal or supporting SM BUS functionality can wake from stop3 ceramic resonator of 32.768 kHz Clock source for iRTC or ICS FTM 2-channel flextimer module selectable input capture, output Oscillator (XOSC2) Loop-control Pierce oscillator Crystal or compare, or buffered edge- or center-aligned PWM on each channel ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz IRTC independent real-time clock, independent power domain, 32 optional clock source for ICS bytes RAM, 32.768 kHz input clock optional output to ICS, hardware Internal Clock Source (ICS) Internal clock source module calendar, hardware compensation due to crystal or temperature containing a frequency-locked-loop (FLL) controlled by internal or characteristics, tamper detection and indicator external reference (XOSC1, XOSC2) precision trimming of internal PCRC 16/32 bit programmable cyclic redundancy check for reference allows 0.2% resolution and 2% deviation over temperature high-speed CRC calculation and voltage supporting CPU/bus frequencies from 1 MHz to 20 MHz MTIM two 8-bit and one 16-bit timers configurable clock inputs System Protection and interrupt generation on overflow PDB programmable delay block optimized for scheduling ADC Watchdog computer operating properly (COP) reset with option to run conversions from dedicated 1 kHz internal clock source or bus clock PCNT position counter working in stop3 mode without waking Low-voltage warning with interrupt CPU can be used to generate waveforms like timer Low-voltage detection with reset or interrupt Input/Output Illegal opcode and illegal address detection with reset Flash block protection 57 GPIOs including one output-only pin Development Support Eight KBI interrupts with selectable polarity Hysteresis and configurable pullup device on all input pins Single-wire background debug interface configurable slew rate and drive strength on all output pins. Breakpoint capability to allow single breakpoint setting during Package Options in-circuit debugging (plus 3 more breakpoints in breakpoint unit) Breakpoint (BKPT) debug module containing three comparators (A, B, 80-pin LQFP, 64-pin LQFP and C) with ability to match addresses in 64 KB space. Each This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2010-2011. All rights reserved.Table of Contents 1 Devices in the MC9S08GW64 Series 3 3.10.1 Control Timing . 29 2 Pin Assignments 6 3.10.2 Timer (TPM/FTM) Module Timing 30 3 Electrical Characteristics 10 3.10.3 SPI Timing 31 3.1 Introduction 10 3.11 Analog Comparator (PRACMP) Electricals . 34 3.2 Parameter Classification 10 3.12 ADC Characteristics 34 3.3 Absolute Maximum Ratings .10 3.13 VREF Characteristics . 39 3.4 Thermal Characteristics 11 3.14 LCD Specifications . 40 3.5 ESD Protection and Latch-Up Immunity 12 3.15 FLASH Specifications . 40 3.6 DC Characteristics 13 4 Ordering Information . 41 3.7 Supply Current Characteristics .23 4.1 Device Numbering System . 41 3.8 External Oscillator (XOSCVLP) Characteristics 26 5 Package Information and Mechanical Drawings 41 3.9 Internal Clock Source (ICS) Characteristics .27 3.10 AC Characteristics 28 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. 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