MC9S08PA16AVTG NXP

Document Number MC9S08PA16 NXP Semiconductors Rev. 4, 03/2020 Data Sheet: Technical Data MC9S08PA16 MC9S08PA16 Series Data MC9S08PA16A and MC9S08PA8A Sheet are recommended for new design Supports: MC9S08PA16(A) and MC9S08PA8(A) Key features Development support Single-wire background debug interface 8-Bit S08 central processor unit (CPU) Breakpoint capability to allow three breakpoints Up to 20 MHz bus at 2.7 V to 5.5 V across operating setting during in-circuit debugging temperature range of -40 C to 105 C for V part and On-chip in-circuit emulator (ICE) debug module -40 C to 125 C for M part. containing two comparators and nine trigger modes Supporting up to 40 interrupt/reset sources Supporting up to four-level nested interrupt Peripherals On-chip memory ACMP - one analog comparator with both positive Up to 16 KB flash read/program/erase over full and negative inputs separately selectable interrupt operating voltage and temperature on rising and falling comparator output filtering Up to 256 byte EEPROM 2-byte erase sector ADC - 12-channel, 12-bit resolution 2.5 s program and erase while executing flash conversion time data buffers with optional Up to 2048 byte random-access memory (RAM) watermark automatic compare function internal Flash and RAM access protection bandgap reference channel operation in stop mode optional hardware trigger Power-saving modes CRC - programmable cyclic redundancy check One low-power stop mode reduced power wait module mode FTM - two flex timer modulators modules including Peripheral clock enable register can disable clocks to one 6-channel and one 2-channel ones 16-bit unused modules, reducing currents allows clocks to counter each channel can be configured for input remain enabled to specific peripherals in stop3 mode capture, output compare, edge- or center-aligned Clocks PWM mode Oscillator (XOSC) - loop-controlled Pierce IIC - One inter-integrated circuit module up to 400 oscillator crystal or ceramic resonator range of kbps multi-master operation programmable slave 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz address supporting broadcast mode and 10-bit Internal clock source (ICS) - containing a frequency- addressing supporting SMBUS and PMBUS locked-loop (FLL) controlled by internal or external MTIM - One modulo timer with 8-bit prescaler and reference precision trimming of internal reference overflow interrupt allowing 1% deviation across temperature range of 0 RTC - 16-bit real timer counter (RTC) C to 70 C and 2% deviation across the whole SCI - two serial communication interface (SCI/ operating temperature up to 20 MHz UART) modules optional 13-bit break full duplex non-return to zero (NRZ) LIN extension support System protection SPI - one 8-bit serial peripheral interface (SPI) Watchdog with independent clock source modules full-duplex or single-wire bidirectional Low-voltage detection with reset or interrupt master or slave mode selectable trip points Illegal opcode detection with reset Illegal address detection with reset NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Input/Output Up to 37 GPIOs including one output-only pin One 8-bit keyboard interrupt module (KBI) Two true open-drain output pins Four, ultra-high current sink pins supporting 20 mA source/sink current Package options 44-pin LQFP 32-pin LQFP 20-pin SOIC 20-pin TSSOP 16-pin TSSOP MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020 2 NXP Semiconductors