Freescale Semiconductor Document Number: MC9S08SE8 Rev. 4, 4/2015 Data Sheet: Technical Data MC9S08SE8 28-Pin SOIC 16-Pin TSSOP Case 751F Case 948F-01 TBD MC9S08SE8 Series 28-Pin PDIP Case 710-02 Covers: MC9S08SE8 MC9S08SE4 Features: SCI Full duplex non-return to zero (NRZ) LIN master extended break generation LIN slave extended 8-Bit HCS08 Central Processor Unit (CPU) break detection wakeup on active edge 20 MHz HCS08 CPU (central processor unit) ADC 10-channel, 10-bit resolution 2.5 s 10 MHz internal bus frequency conversion time automatic compare function HC08 instruction set with added BGND 1.7 mV/C temperature sensor internal bandgap Support for up to 32 interrupt/reset sources reference channel runs in stop3 On-Chip Memory TPMx One 2-channel (TPM1) and one 1-channel Up to 8 KB of on-chip in-circuit programmable flash (TPM2) 16-bit timer/pulse-width modulator (TPM) memory with block protection and security options modules selectable input capture, output compare, and Up to 512 bytes of on-chip RAM edge-aligned PWM capability on each channel timer Power-Saving Modes module may be configured for buffered, centered PWM Wait plus two stops (CPWM) on all channels Clock Source Options KBI 8-pin keyboard interrupt module Oscillator (XOSC) Loop-control Pierce oscillator RTC Real-time counter with binary- or crystal or ceramic resonator range of 31.25 kHz to decimal-based prescaler 38.4 kHz or 1 MHz to 16 MHz Input/Output Internal Clock Source (ICS) Internal clock source Software selectable pullups on ports when used as inputs module containing a frequency-locked-loop (FLL) Software selectable slew rate control on ports when used controlled by internal or external reference precision as outputs trimming of internal reference allows 0.2% resolution Software selectable drive strength on ports when used as and 2% deviation over temperature and voltage outputs supports bus frequencies from 1 MHz to 10 MHz. Master reset pin and power-on reset (POR) System Protection Internal pullup on RESET, IRQ, and BKGD/MS pins to Optional computer operating properly (COP) reset with reduce customer system cost option to run from independent 1 kHz internal clock Package Options source or the bus clock 28-pin PDIP Low voltage detection 28-pin SOIC Illegal opcode detection with reset 16-pin TSSOP Illegal address detection with reset Development Support Single-wire background debug interface Breakpoint capability to allow single breakpoint setting during in-circuit debugging Peripherals This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2008-2009, 2015. All rights reserved.Table of Contents 1 MCU Block Diagram .3 3.8 Internal Clock Source (ICS) Characteristics 20 2 Pin Assignments 4 3.9 ADC Characteristics 22 3 Electrical Characteristics .6 3.10 AC Characteristics 25 3.1 Parameter Classification .6 3.10.1 Control Timing . 25 3.2 Absolute Maximum Ratings 6 3.10.2 TPM/MTIM Module Timing 26 3.3 Thermal Characteristics .7 3.11 Flash Specifications . 27 3.4 ESD Protection and Latch-Up Immunity .8 4 Ordering Information . 27 3.5 DC Characteristics .9 4.1 Package Information 28 3.6 Supply Current Characteristics .15 4.2 Mechanical Drawings 28 3.7 External Oscillator (XOSC) Characteristics .19 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: freescale.com The following revision history table summarizes changes contained in this document. Revision Date Description of Changes 1 10/8/2008 Initial public released. 2 1/16/2009 In Table 8, added the Max. of S2I and S3I in 0105 C changed the Max. of S2I and DD DD DD S3I in 085 C changed the typical of S2I and S3I changed the S23I to P. DD DD DD DDRTI 3 4/7/2009 Added I in the Table 7. OZTOT Changed V to V , V to V . DDAD DDA SSAD SSA Updated Table 9, Table 10, Table 11, and Table 12. Updated Figure 13 and Figure 14. 4 4/10/2015 Updated Table 9. Related Documentation Find the most current versions of all documents at: