Freescale Semiconductor Document Number: MC9S08SF4 Rev. 4, 9/2011 Data Sheet: Technical Data MC9S08SF4 20-Pin TSSOP 16-Pin TSSOP MC9S08SF4 Series Case 948E Case 948F Features Peripherals IPC Prioritize interrupt sources besides inherent 8-Bit S08 Central Processor Unit (CPU) CPU interrupt table support up to 32 interrupt sources Up to 40 MHz CPU at 2.7 V to 5.5 V across temperature and up to 4-level preemptive interrupt nesting range of 40 C to 125 C ADC 8-channel, 10-bit resolution 2.5 s conversion HC08 instruction set with added BGND instruction time automatic compare function temperature sensor Support for up to 32 interrupt/reset sources internal bandgap reference channel operation in stop On-Chip Memory fully functional from 2.7 V to 5.5 V 4 KB flash read/program/erase over full operating TPM One 40 MHz 6-channel and one 40 MHz voltage and temperature 1-channel timer/pulse-width modulators (TPM) 128-byte random-access memory (RAM) modules selectable input capture, output compare, or Security circuitry to prevent unauthorized access to buffered edge- or center-aligned PWM on each channel RAM and flash contents MTIM16 Two 16-bit modulo timers Power-Saving Modes PWT Two 16-bit pulse width timers (PWT) Two low power stop modes reduced power wait mode selectable driving clock, positive/negative/period Allows clocks to remain enabled to specific peripherals capture in stop3 mode PRACMP Two programmable reference analog Clock Source Options comparators with eight optional inputs for both positive Internal Clock Source (ICS) Internal clock source and negative inputs 32-level internal reference voltages module containing a frequency-locked-loop (FLL) scaled by selectable reference inputs controlled by an internal or external reference precision IIC Inter-integrated circuit bus module capable of trimming of internal reference allows 0.2% resolution operation up to 100 kbps with maximum bus loading and 1% deviation over 070 C and voltage, 2% multi-master operation programmable slave address deviation over 4085 C and voltage, or 3% deviation interrupt-driven byte-by-byte data transfer broadcast over 40125 C and voltage supporting bus mode 10-bit addressing frequencies up to 20 MHz KBI 4-pin keyboard interrupt module with software System Protection selectable polarity on edge or edge/level modes Watchdog computer operating properly (COP) reset FDS Shut down output pin upon fault detection the with option to run from dedicated 1 kHz internal clock fault sources can be optional enabled separately the source or bus clock output pin can be configured as output 1,0 and high Low-voltage detection with reset or interrupt selectable impedance when a fault occurs based on module trip points configuration Illegal opcode detection with reset Input/Output Illegal address detection with reset 18 GPIOs including one input-only pin and one Flash block protection output-only pin Development Support Hysteresis and configurable pullup device on all input Single-wire background debug interface pins schmitt trigger on PWT input pins configurable Breakpoint capability to allow single breakpoint setting slew rate and drive strength on all output pins. during in-circuit debugging (plus two more breakpoints) Package Options On-chip in-circuit emulator (ICE) debug module 16-pin TSSOP containing two comparators and nine trigger modes 20-pin TSSOP This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2009-2011. All rights reserved.Table of Contents 1 MCU Block Diagram . 3 3.11 PRACMP Characteristics 21 2 Pin Assignments . 3 3.12 Flash Specifications 22 3 Electrical Characteristics . 5 4 Ordering Information 23 3.1 Introduction . 5 5 Package Information 23 3.2 Parameter Classification . 5 5.1 Mechanical Drawings .23 3.3 Absolute Maximum Ratings . 5 3.4 Thermal Characteristics 6 3.5 ESD Protection and Latch-Up Immunity . 7 3.6 DC Characteristics 8 3.7 Supply Current Characteristics . 14 3.8 ICS Characteristics 16 3.9 AC Characteristics . 17 3.9.1 Control Timing . 18 3.9.2 Timer/PWM (TPM) Module Timing . 19 3.10 ADC Characteristics . 20 Revision History The following revision history table summarizes changes contained in this document. Revision Date Description of Changes 2 4/30/2009 Initial public release. 3 8/18/2009 Polished. 4 9/19/2011 Updated V in the Table 12. AIN Related Documentation Reference Manual (MC9S08SF4RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08SF4 Series MCU Data Sheet, Rev. 4 2 Freescale Semiconductor