Freescale Semiconductor, Inc.
Product Brief
MPC535PB/D
Rev. 0, 2/2003
MPC535/MPC536
Product Brief
This document provides an overview of the MPC535/MPC536 microcontrollers, including a
block diagram showing the major modular components, sections that list the major features,
and differences between the MPC535/MPC536 and the MPC555. The MPC535 and MPC536
devices are members of the Motorola MPC500 RISC Microcontroller family. The parts herein
will be referred to only as MPC535 unless specific parts need to be referenced.
Table 1. MPC535/MPC536 Features
Device Flash Code Compression
MPC535 1 Mbyte Code compression not supported
MPC536 1 Mbyte Code compression supported
1 Introduction
The MPC535 device offers the following features:
PowerPC core with a floating point unit (FPU) and a burst buffer controller (BBC)
Unified system integration unit (USIU), a flexible memory controller, and improved
interrupt controller
1 Mbyte of Flash memory (UC3F)
Typical endurance of 100,000 write/erase cycles @ 25C
Typical data retention of 100 years @ 25C
36 Kbytes of static RAM (two CALRAM modules)
8 Kbytes of normal access or overlay access (sixteen 512-byte regions)
4 Kbytes in CALRAM A, 4 Kbytes in CALRAM B
A 22-timer channel modular I/O system (MIOS14)
Same as MIOS1 plus a real-time clock sub-module (MRTCSM), 4 counter
sub-modules (MCSM), and 4 PWM sub-modules (MPWMSM)
One TouCAN module (TouCAN_B)
One enhanced queued analog to digital converter (QADC64E A).
One queued serial multi-channel module (QSMCM A) which contains a queued
serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)
-40C 85C ambient temperature
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Block Diagram
Debug features:
A Nexus debug port (class 3) IEEE-ISTO 5001-1999
JTAG and background debug mode (BDM)
Packaging and Electrical
1.1 Block Diagram
Figure 1 is a block diagram of the MPC535.
512 Kbytes 512 Kbytes
JTAG
Flash Flash
Burst
Buffer
Controller 2
U-Bus
DECRAM
E-Bus
(4Kbytes)
USIU
MPC500
READI
4 Kbyte CALRAM B
Core
+
4 Kbyte Overlay
FP
L2U
L-Bus
32 Kbyte CALRAM A
28 Kbytes SRAM
No Overlay
4 Kbyte Overlay
UIMB
QADC64E
QSMCM
I/F
IMB3
Tou
MIOS14
CAN
Figure 1. MPC535 Block Diagram
1.2 Detailed Feature List
The MPC535 key features are explained in the following sections.
1.2.1 High Performance CPU System
Fully static design
Four major power saving modes
On, doze, sleep, deep-sleep and power-down
2 MPC535/MPC536 Product Brief MOTOROLA
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