Freescale Semiconductor Document Number: MSC7116 Rev. 13, 4/2008 Data Sheet MSC7116 Low-Cost 16-bit DSP with MAP-BGA400 DDR Controller and 10/100 17 mm 17 mm Mbps Ethernet MAC StarCore SC1400 DSP extended core with one SC1400 DSP Multi-channel DMA controller with 32 time-multiplexed core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte unidirectional channels, priority-based time-multiplexing instruction cache (ICache), four-entry write buffer, programmable between channels using 32 internal priority levels, fixed- or interrupt controller (PIC), and low-power Wait and Stop round-robin-priority operation, major-minor loop structure, and processing modes. DONE or DRACK protocol from requesting units. 192 Kbyte M2 memory for critical data and temporary data Two independent TDM modules with independent receive and buffering. transmit, programmable sharing of frame sync and clock, 8 Kbyte boot ROM. programmable word size (8 or 16-bit), hardware-base AHB-Lite crossbar switch that allows parallel data transfers A-law/-law conversion, up to 50 Mbps data rate per TDM, up to between four master ports and six slave ports, where each port 128 channels, with glueless interface to E1/T1 frames and MVIP, connects to an AHB-Lite bus fixed or round robin priority SCAS, and H.110 buses. programmable at each slave port programmable bus parking at Ethernet controller with support for 10/100 Mbps MII/RMII each slave port low power mode. designed to comply with IEEE Std. 802.3, 802.3u, 802.3x, Internal PLL generates up to 266 MHz clock for the SC1400 core and 802.3ac with internal receive and transmit FIFOs and a and up to 133 MHz for the crossbar switch, DMA channels, M2 FIFO controller direct access to internal memories via its own memory, and other peripherals. DMA controller full and half duplex operation programmable Clock synthesis module provides predivision of PLL input clock maximum frame length virtual local area network (VLAN) tag independent clocking of the internal timers and DDR module and priority support retransmission of transmit FIFO following programmable operation in the SC1400 low power Stop mode collision CRC generation and verification for inbound and independent shutdown of different regions of the device. outbound packets and address recognition including Enhanced 16-bit wide host interface (HDI16) provides a glueless promiscuous, broadcast, individual address. hash/exact match, connection to industry-standard microcomputers, and multicast hash match. microprocessors, and DSPs and can also operate with an 8-bit host UART with full-duplex operation up to 5.0 Mbps. data bus, making if fully compatible with the DSP56300 HI08 Up to 41 general-purpose input/output (GPIO) ports. 2 from the external host side. I C interface that allows booting from EEPROM devices up to 1 DDR memory controller that supports byte enables for up to a Mbyte. 32-bit data bus glueless interface to 133 MHz 14-bit page mode Two quad timer modules, each with sixteen configurable 16-bit DDR-RAM 14-bit external address bus supporting up to 1 Gbyte timers. and 16-bit or 32-bit external data bus. fieldBIST unit detects and provides visibility into unlikely field Programmable memory interface with independent read buffers, failures for systems with high availability to ensure structural programmable predictive read feature for each buffer, and a write integrity, that the device operates at the rated speed, is free from buffer. reliability defects, and reports diagnostics for partial or complete System control unit performs software watchdog timer function device inoperability. includes programmable bus time-out monitors on AHB-Lite slave Standard JTAG interface allows easy integration to system buses includes bus error detection and programmable time-out firmware and internal on-chip emulation (OCE10) module. monitors on AHB-Lite master buses and has address Optional booting external host via 8-bit or 16-bit access through 2 out-of-range detection on each crossbar switch buses. the HDI16, I C, or SPI using in the boot ROM to access serial SPI Event port collects and counts important signal events including Flash/EEPROM devices different clocking options during boot DMA and interrupt requests and trigger events such as interrupts, with the PLL on or off using a variety of input frequency ranges. breakpoints, DMA transfers, or wake-up events units operate independently, in sequence, or triggered externally can be used standalone or with the OCE10. Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Table of Contents 1 Pin Assignments 4 Figure 8. TDM Receive Signals . 28 1.1 MAP-BGA Ball Layout Diagrams 4 Figure 9. TDM Transmit Signals 29 1.2 Signal List By Ball Location .6 Figure 10. Ethernet Receive Signal Timing . 29 2 Electrical Characteristics 17 Figure 11. Ethernet Receive Signal Timing . 30 2.1 Maximum Ratings .17 Figure 12. Asynchronous Input Signal Timing . 30 2.2 Recommended Operating Conditions 18 Figure 13. Serial Management Channel Timing . 31 2.3 Thermal Characteristics 19 Figure 14. Read Timing Diagram, Single Data Strobe 33 2.4 DC Electrical Characteristics 19 Figure 15. Read Timing Diagram, Double Data Strobe 33 2.5 AC Timings 21 Figure 16. Write Timing Diagram, Single Data Strobe . 34 3 Hardware Design Considerations 41 Figure 17. Write Timing Diagram, Double Data Strobe 34 3.1 Thermal Design Considerations 41 Figure 18. Host DMA Read Timing Diagram, HPCR OAD = 0 35 3.2 Power Supply Design Considerations 42 Figure 19. Host DMA Write Timing Diagram, HPCR OAD = 0 35 3.3 Estimated Power Usage Calculations 49 Figure 20. I2C Timing Diagram 36 3.4 Reset and Boot .51 Figure 21. UART Input Timing . 37 3.5 DDR Memory System Guidelines .54 Figure 22. UART Output Timing . 37 4 Ordering Information 57 Figure 23. EE Pin Timing . 37 5 Package Information 58 Figure 24. EVNT Pin Timing 38 6 Product Documentation .58 Figure 25. GPI/GPO Pin Timing . 38 7 Revision History .59 Figure 26. Test Clock Input Timing Diagram 39 Figure 27. Boundary Scan (JTAG) Timing Diagram 40 List of Figures Figure 28. Test Access Port Timing Diagram . 40 Figure 1. MSC7116 Block Diagram . 3 Figure 29. TRST Timing Diagram 40 Figure 2. MSC7116 Molded Array Process-Ball Grid Array Figure 30. Voltage Sequencing Case 1 43 (MAP-BGA), Top View . 4 Figure 31. Voltage Sequencing Case 2 44 Figure 3. MSC7116 Molded Array Process-Ball Grid Array Figure 32. Voltage Sequencing Case 3 45 (MAP-BGA), Bottom View 5 Figure 33. Voltage Sequencing Case 4 46 Figure 4. Timing Diagram for a Reset Configuration Write 25 Figure 34. Voltage Sequencing Case 5 47 Figure 5. DDR DRAM Input Timing Diagram 26 Figure 35. PLL Power Supply Filter Circuits 48 Figure 6. DDR DRAM Output Timing Diagram . 27 Figure 36. SSTL Termination Techniques 54 Figure 7. DDR DRAM AC Test Load . 28 Figure 37. SSTL Power Value . 55 MSC7116 Data Sheet, Rev. 13 2 Freescale Semiconductor