Freescale Semiconductor Document Number: MSC8122 Rev. 16, 12/2008 Data Sheet: MSC8122 FC PBGA431 20 mm 20 mm Quad Digital Signal Processor Four StarCore SC140 DSP extended cores, each with an SC140 8 memory banks for external memories, and 2 memory banks for DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte IPBus peripherals and internal memories. total), 16 way 16 Kbyte instruction cache (ICache), four-entry Multi-channel DMA controller with 16 time-multiplexed single write buffer, external cache support, programmable interrupt channels, up to four external peripherals, DONE or DRACK controller (PIC), local interrupt controller (LIC), and low-power protocol for two external peripherals,.service for up to 16 internal Wait and Stop processing modes. requests from up to 8 internal FIFOs per channel, FIFO generated 475 Kbyte M2 memory for critical data and temporary data watermarks and hungry requests, priority-based buffering. time-multiplexing between channels using 16 internal priority 4 Kbyte boot ROM. levels or round-robin time-multiplexing between channels, M2-accessible multi-core MQBus connecting the M2 memory flexible channel configuration with connection to local bus or with all four cores, operating at the core frequency, with data bus system bus, and flyby transfer support that bypasses the FIFO. access of up to 128-bit reads and up to 64-bit writes, central Up to four independent TDM modules with programmable word efficient round-robin arbiter for core access to the bus, and atomic size (2, 4, 8, or 16-bit), hardware-base A-law/-law conversion, operation control of M2 memory access by the cores and the local up to 128 Mbps data rate for all channels, with glueless interface bus. to E1 or T1 framers, and can interface with H-MVIP/H.110 Internal PLL configured are reset by configuration signal values. devices, TSI, and codecs such as AC-97. 60x-compatible system bus with 64 or 32 bit data and 32-bit Ethernet controller with support for 10/100 Mbps MII/RMII/SMII address bus, support for multi-master designs, four-beat burst including full- and half-duplex operation, full-duplex flow transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 controls, out-of-sequence transmit queues, programmable bits controlled by the internal memory controller,.access to maximum frame length including jumbo frames and VLAN tags external memory or peripherals, access by an external host to and priority, retransmission after collision, CRC generation and internal resources, slave support with direct access to internal verification of inbound/outbound packets, address recognition resources including M1 and M2 memories, and on-device (including exact match, broadcast address, individual hash check, arbitration for up to four master devices. group hash check, and promiscuous mode), pattern matching, Direct slave interface (DSI) using a 32/64-bit slave host interface insertion with expansion or replacement for transmit frames, with 2125 bit addressing and 32/64-bit data transfers, direct VLAN tag insertion, RMON statistics, local bus master DMA for access by an external host to internal and external resources, descriptor fetching and buffer access, and optional multiplexing synchronous or asynchronous accesses with burst capability in with GPIO (MII/RMII/SMII) or DSI/system bus signals lines synchronous mode, dual or single strobe mode, write and read (MII/RMII). buffers to improve host bandwidth, byte enable signals for UART with full-duplex operation up to 6.25 Mbps. 1/2/4/8-byte write granularity, sliding window mode for access Up to 32 general-purpose input/output (GPIO) ports. 2 using a reduced number of address pins, chip ID decoding to I C interface that allows booting from EEPROM devices. allow one CS signal to control multiple DSPs, broadcast mode to Two timer modules, each with sixteen configurable 16-bit timers. write to multiple DSPs, and big-endian/little-endian/munged Eight programmable hardware semaphores. support. Global interrupt controller (GIC) with interrupt consolidation and Three mode signal multiplexing: 64-bit DSI and 32-bit system routing to INT OUT, NMI OUT, and the cores thirty-two virtual bus, 32-bit DSI and 64-bit system bus, or 32-bit DSI and 32-bit maskable interrupts (8 per core) and four virtual NMI (one per system bus. core) that can be generated by a simple write access. Flexible memory controller with three UPMs, a GPCM, a Optional booting external memory, external host, UART, TDM, 2 page-mode SDRAM machine, glueless interface to a variety of or I C. memories and devices, byte enables for 64- or 32-bit bus widths, Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Table of Contents 1 Pin Assignments 4 Figure 10.Internal Tick Spacing for Memory Controller Signals . 22 1.1 FC-PBGA Ball Layout Diagrams .4 Figure 11.SIU Timing Diagram . 25 1.2 Signal List By Ball Location .7 Figure 12.CLKOUT and CLKIN Signals . 26 2 Electrical Characteristics 13 Figure 13.DMA Signals . 27 2.1 Maximum Ratings .13 Figure 14.Asynchronous Single- and Dual-Strobe Modes Read 2.2 Recommended Operating Conditions 14 Timing Diagram . 29 2.3 Thermal Characteristics 14 Figure 15.Asynchronous Single- and Dual-Strobe Modes Write 2.4 DC Electrical Characteristics 15 Timing Diagram . 30 2.5 AC Timings 16 Figure 16.Asynchronous Broadcast Write Timing Diagram 30 3 Hardware Design Considerations 39 Figure 17.DSI Synchronous Mode Signals Timing Diagram . 31 3.1 Start-up Sequencing Recommendations .39 Figure 18.TDM Inputs Signals 32 3.2 Power Supply Design Considerations 40 Figure 19.TDM Output Signals . 32 3.3 Connectivity Guidelines 41 Figure 20.UART Input Timing 33 3.4 External SDRAM Selection 42 Figure 21.UART Output Timing . 33 3.5 Thermal Considerations 43 Figure 22.Timer Timing . 34 4 Ordering Information 43 Figure 23.MDIO Timing Relationship to MDC 34 5 Package Information 44 Figure 24.MII Mode Signal Timing . 35 6 Product Documentation .44 Figure 25.RMII Mode Signal Timing . 35 7 Revision History .45 Figure 26.SMII Mode Signal Timing 36 Figure 27.GPIO Timing . 37 List of Figures Figure 28.EE Pin Timing 37 Figure 1. MSC8122 Block Diagram 3 Figure 29.Test Clock Input Timing Diagram 38 Figure 2. StarCore SC140 DSP Extended Core Block Diagram 3 Figure 30.Boundary Scan (JTAG) Timing Diagram 38 Figure 3. MSC8122 Package, Top View 5 Figure 31.Test Access Port Timing Diagram . 39 Figure 4. MSC8122 Package, Bottom View 6 Figure 32.TRST Timing Diagram 39 Figure 5. Overshoot/Undershoot Voltage for V and V . 16 IH IL Figure 33.Core Power Supply Decoupling . 40 Figure 6. Start-Up Sequence: V and V Raised Together 17 DD DDH Figure 34.V Bypass . 41 CCSYN Figure 7. Start-Up Sequence: V Raised Before V with CLKIN DD DDH Figure 35.MSC8122 Mechanical Information, 431-pin FC-PBGA Started with V . 17 DDH Package . 44 Figure 8. Power-Up Sequence for V and V /V . 18 DDH DD CCSYN Figure 9. Timing Diagram for a Reset Configuration Write . 21 MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 2 Freescale Semiconductor