Freescale Semiconductor Document Number: MSC8144
Rev. 16, 5/2010
Data Sheet
MSC8144
FC-PBGA783
29 mm 29 mm
Quad Core Digital Signal
Processor
Four StarCore SC3400 DSP subsystems, each with an SC3400 The two Ethernet controllers support 10/100/1000 Mbps
DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, operations via MII/RMII/SMII/RGMII/SGMII and the SGMII
memory management unit (MMU), extended programmable protocol using a 4-pin SerDes interface at 1000 Mbps data rate
interrupt controller (EPIC), two general-purpose 32-bit timers, only.
debug and profiling support, and low-power Wait and Stop The ATM controller supports UTOPIA level II 8/16 bits at
processing modes. 25/50 MHz in UTOPIA/POS mode with adaptation layer
Chip-level arbitration and system (CLASS) that provides full support AAL0, AAL2, and AAL5.
fabric non-blocking arbitration between the processing elements PCI designed to comply with the PCI specification revision 2.2 at
and other initiators and the M2 memory, DDR SRAM controller, 33 MHz or 66 MHz with access to all PCI address spaces.
device configuration control and status registers, and other Serial RapidIO 1x/4x endpoint corresponds to Specification 1.2
targets. of the RapidIO trade association, and supports read, write,
128 Kbyte L2 shared instruction cache. messages, doorbells, and maintenance accesses in inbound mode,
512 Kbyte M2 memory for critical data and temporary data and messages and doorbells in outbound mode.
buffering. I/O interrupt concentrator consolidates all chip maskable interrupt
10 Mbyte 128-bit wide M3 memory. and non-maskable interrupt sources and routes them to
96 Kbyte boot ROM. INT_OUT, NMI_OUT, and the cores.
Three input clocks (shared, global, and differential). UART that permits full-duplex operation with a bit rate of up to
Four PLLs (system, core, global, and serial RapidIO). 6.25 Mbps.
DDR controller with up to a 200 MHz clock (400 MHz data rate), Serial peripheral interface (SPI).
16/32 bit data bus, supporting up to 1 Gbyte in up to two banks Four timer modules, each with four configurable16-bit timers.
and support for DDR1 and DDR2. Four software watchdog timer (SWT) modules.
DMA controller with 16 bidirectional channels with up to 1024 Up to 32 general-purpose input/output (GPIO) ports, 16 of which
buffer descriptors, and programmable priority, buffer, and can be configured as maskable interrupt inputs.
2
multiplexing configuration. I C interface that allows booting from EEPROM devices.
Up to eight independent TDM modules with programmable word Eight programmable hardware semaphores.
size (2, 4, 8, or 16-bit), hardware-base A-law/-law conversion, Thirty two virtual maskable interrupts and one virtual NMI that
up to 128 Mbps data rate for all channels, with glueless interface can be generated by a simple write access.
2
to E1 or T1 framers, and can interface with H-MVIP/H.110 Optional booting via serial RapidIO port, PCI, I C, SPI, or
devices, TSI, and codecs such as AC-97. Ethernet interfaces.
QUICC Engine technology subsystem with dual RISC
Note: This document supports mask set M31H.
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
RAM, supporting three communication controllers with one ATM
and two Gigabit Ethernet interfaces, to offload scheduling tasks
from the DSP cores.
20072010 Freescale Semiconductor, Inc.
Table of Contents
1 Pin Assignments and Reset States. . . . . . . . . . . . . . . . . . . . . .4 Figure 12.Transmitter Output Compliance Mask . . . . . . . . . . . . . . 46
1.1 FC-PBGA Ball Layout Diagrams. . . . . . . . . . . . . . . . . . .4 Figure 13.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 48
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6 Figure 14.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 49
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 15.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 16.PCI Input AC Timing Measurement Conditions. . . . . . . 51
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27 Figure 17.PCI Output AC Timing Measurement Condition . . . . . . 51
2.3 Default Output Driver Characteristics . . . . . . . . . . . . . .28 Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 20.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29 Figure 21.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.6 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 22.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .64 Figure 23.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .64 Figure 24.MII Management Interface Timing. . . . . . . . . . . . . . . . . 55
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .66 Figure 25.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3 Clock and Timing Signal Board Layout Considerations 67 Figure 26.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.4 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .67 Figure 27.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Figure 28.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . 57
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Figure 29.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Figure 30.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 58
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Figure 31.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 59
Figure 32.ATM/UTOPIA/POS AC Test Load . . . . . . . . . . . . . . . . . 60
List of Figures
Figure 33.ATM/UTOPIAPOS AC Timing (External Clock) . . . . . . . 60
Figure 1. MSC8144 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 34.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram 3
Figure 35.SPI AC Timing in Slave Mode (External Clock). . . . . . . 61
Figure 3. MSC8144 FC-PBGA Package, Top View . . . . . . . . . . . . 4
Figure 36.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 62
Figure 4. MSC8144 FC-PBGA Package, Bottom View . . . . . . . . . 5
Figure 37.Asynchronous Signal Timing . . . . . . . . . . . . . . . . . . . . . 62
Figure 5. SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31
Figure 38.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 6. Start-Up Sequence with V Raised Before V with
DD DDIO Figure 39.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 63
CLKIN Started with V . . . . . . . . . . . . . . . . . . . . . . . 35
DDIO Figure 40.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 7. Timing for a Reset Configuration Write . . . . . . . . . . . . . 38
Figure 41.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 8. Timing for t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DDKHMH Figure 42.V , V and V Power-on Sequence . . . . . 65
DDM3 DDM3IO 25M3
Figure 9. DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41
Figure 44.MSC8144 Mechanical Information, 783-ball FC-PBGA
Figure 10.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 11.Differential V of Transmitter or Receiver . . . . . . . . . . 42
PP
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
2 Freescale Semiconductor