Document Number: MSC8156E Freescale Semiconductor Rev. 5, 07/2013 Data Sheet: Technical Data MSC8156E Six-Core Digital Signal Processor with Security FC-PBGA783 29 mm 29 mm Six StarCore SC3850 DSP subsystems, each with an SC3850 interface to E1 or T1 framers that can interface with DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, H-MVIP/H.110 devices, TSI, and codecs such as AC-97. unified 512 Kbyte L2 cache configurable as M2 memory in High-speed serial interface that supports two Serial RapidIO 64 Kbyte increments, memory management unit (MMU), interfaces, one PCI Express interface, and two SGMII interfaces extended programmable interrupt controller (EPIC), two (multiplexed). The Serial RapidIO interfaces support 1x/4x general-purpose 32-bit timers, debug and profiling support, operation up to 3.125 Gbaud with a single messaging unit and two low-power Wait, Stop, and power-down processing modes, and DMA units. The PCI Express controller supports 32- and 64-bit ECC/EDC support. addressing, x4, x2, and x1 link. Chip-level arbitration and switching system (CLASS) that QUICC Engine technology subsystem with dual RISC provides full fabric non-blocking arbitration between the cores processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction and other initiators and the M2 memory, shared M3 memory, RAM, supporting two communication controllers for two Gigabit DDR SRAM controllers, device configuration control and status Ethernet interfaces (RGMII or SGMII), to offload scheduling registers, MAPLE-B, and other targets. tasks from the DSP cores, and an SPI. 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can I/O Interrupt Concentrator consolidates all chip maskable be turned off to save power. interrupt and non-maskable interrupt sources and routes then to 96 Kbyte boot ROM. INT OUT, NMI OUT, and the cores. Three input clocks (one global and two differential). UART that permits full-duplex operation with a bit rate of up to Five PLLs (three global and two Serial RapidIO PLLs). 6.25 Mbps. Multi-Accelerator Platform Engine for Baseband (MAPLE-B) Two general-purpose 32-bit timers for RTOS support per SC3850 with a programmable system interface, Turbo decoding, Viterbi core, four timer modules with four 16-bit fully programmable decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B timers, and eight software watchdog timers (SWT). can be disabled when not required to reduce overall power Eight programmable hardware semaphores. consumption. Up to 32 virtual interrupts and a virtual NMI asserted by simple Security Engine (SEC) optimized to process all the algorithms write access. 2 associated with IPSec, IKE, SSL/TLS, 3GPP, and LTE using 4 I C interface. crypto-channels with multi-command descriptor chains, Up to 32 GPIO ports, sixteen of which can be configured as integrated controller for assignment of the eight execution units external interrupts. (PKEU, DEU, AESU, AFEU, MDEU, KEU, SNOW, and the Boot interface options include Ethernet, Serial RapidIO interface, 2 random number generator (RNG), and XOR engine to accelerate I C, and SPI. parity checking for RAID storage applications. Supports standard JTAG interface Two DDR controllers with up to a 400 MHz clock (800 MHz data Low power CMOS design, with low-power standby and rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to power-down modes, and optimized power-management circuitry. four banks (two per controller) and support for DDR2 and DDR3. 45 nm SOI CMOS technology. DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 20082013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignment .4 Figure 11.DDR2 and DDR3 SDRAM Interface Input Timing 1.1 FC-PBGA Ball Layout Diagram 4 Diagram . 38 1.2 Signal List By Ball Location .5 Figure 12.MCK to MDQS Timing 39 2 Electrical Characteristics 24 Figure 13.DDR SDRAM Output Timing . 40 2.1 Maximum Ratings .24 Figure 14.DDR2 and DDR3 Controller Bus AC Test Load . 40 2.2 Recommended Operating Conditions 25 Figure 15.DDR2 and DDR3 SDRAM Differential Timing 2.3 Thermal Characteristics 25 Specifications 40 2.4 CLKIN Requirements 26 Figure 16.Differential Measurement Points for Rise and Fall Time 42 2.5 DC Electrical Characteristics 26 Figure 17.Single-Ended Measurement Points for Rise and Fall Time 2.6 AC Timing Characteristics .37 Matching 42 3 Hardware Design Considerations 55 Figure 18.Single Frequency Sinusoidal Jitter Limits . 45 3.1 Power Supply Ramp-Up Sequence 55 Figure 19.SGMII AC Test/Measurement Load 45 3.2 PLL Power Supply Design Considerations 58 Figure 20.TDM Receive Signals 47 3.3 Clock and Timing Signal Board Layout Considerations 59 Figure 21.TDM Transmit Signals 48 3.4 SGMII AC-Coupled Serial Link Connection Example 59 Figure 22.TDM AC Test Load 48 3.5 Connectivity Guidelines 60 Figure 23.Timer AC Test Load 49 3.6 Guide to Selecting Connections for Remote Power Figure 24.MII Management Interface Timing . 50 Supply Sensing .64 Figure 25.RGMII AC Timing and Multiplexing 51 4 Ordering Information 66 Figure 26.SPI AC Test Load . 52 5 Package Information 67 Figure 27.SPI AC Timing in Slave Mode (External Clock) . 52 6 Product Documentation .68 Figure 28.SPI AC Timing in Master Mode (Internal Clock) 52 7 Revision History .68 Figure 29.Test Clock Input Timing . 54 Figure 30.Boundary Scan (JTAG) Timing . 54 Figure 31.Test Access Port Timing 54 List of Figures Figure 32.TRST Timing . 55 Figure 1. MSC8156E Block Diagram . 3 Figure 33.Supply Ramp-Up Sequence with V Ramping Before DD Figure 2. StarCore SC3850 DSP Subsystem Block Diagram 3 V and CLKIN Starting With V . 55 DDIO DDIO Figure 3. MSC8156E FC-PBGA Package, Top View . 4 Figure 34.Supply Ramp-Up Sequence . 57 Figure 4. Differential Voltage Definitions for Transmitter or Figure 35.Reset Connection in Functional Application . 57 Receiver 28 Figure 36.Reset Connection in Debugger Application 57 Figure 5. Receiver of SerDes Reference Clocks . 30 Figure 37.PLL Supplies . 58 Figure 6. SerDes Transmitter and Receiver Reference Circuits 31 Figure 38.SerDes PLL Supplies 59 Figure 7. Differential Reference Clock Input DC Requirements Figure 39.4-Wire AC-Coupled SGMII Serial Link Connection (External DC-Coupled) . 32 Example . 59 Figure 8. Differential Reference Clock Input DC Requirements Figure 40.MSC8156E Mechanical Information, 783-ball FC-PBGA (External AC-Coupled) . 32 Package . 67 Figure 9. Single-Ended Reference Clock Input DC Requirements 33 Figure 10.SGMII Transmitter DC Measurement Circuit . 35 MSC8156E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 5 2 Freescale Semiconductor