QorIQ P Series Processors QorIQ P1012 and P1021 Communications Processors The QorIQ P1 family, which includes the P1012 and P1021 communications processors, offers the value of smart integration and efficient power intelligence for a wide variety of applications in the networking, telecom, defense and industrial markets. Based on 45 nm technology for low power, the P1012 and P1021 processors provide single- and dual-core options, from 533 MHz 800 MHz, along with advanced security and a rich set of interfaces. The P1012 and P1021 processors are ideally suited for multiservice gateways, Ethernet switch controllers, wireless LAN access points and highperformance general-purpose control processor applications with tight thermal constraints. The P1012 and P1021 processors are pincompatible with the QorIQ P1011, P1020 and P2 platform products, offering a six-chip range of cost-effective solutions. Scaling from a single core at 533 MHz (P1012) to a dual core at 1.2 GHz per core (P2020), the combined QorIQ platforms deliver an impressive 4.5x aggregate frequency range. The P1012 and P1021 platforms are fully software compatible, both featuring the e500 Power Architecture core and peripherals, as well as being fully software compatible with the earlier PowerQUICC processors. This enables customers to create a product with multiple performance points from a single board design. The QorIQ P1021 dual-core processor supports both symmetric and asymmetric processing, enabling customers to further optimize their design with the same applications running on each core or serialize your application using the cores for different processing tasks. QorIQ P1012 and P1021 Block Diagram QorIQ P1012 and P1021 Block Diagram QorIQ P1012 and P1021 Block Diagram Not on P1012 Not on P1012 Security DDR2/DDR3 Power Architecture Power Architecture Acceleration SDRAM Controller Security DDR2/DDR3 e500 Core e500 Core Power Architecture Power Architecture 256 KB Acceleration SDRAM Controller e500 Core e500 Core L2 Cache 256 KB XOR 32 KB 32 KB 32 KB 32 KB 2 L2 Cache DUART, 2x I C, Timers, XOR L1 I Cache L1 D Cache L1 I Cache L1 D Cache 32 KB 32 KB 32 KB 32 KB Interrupt Control, 2 DUART, 2x I C, Timers, L1 I Cache L1 D Cache L1 I Cache L1 D Cache SD/MMC, SPI, Interrupt Control, USB 2.0/ULPI SD/MMC, SPI, USB 2.0/ULPI Coherency Module Coherency Module Enhanced Local Bus System Bus Controller (eLBC) Enhanced Local Bus System Bus Controller (eLBC) 3x On-Chip NetworOn-Chip Networkk Gigabit QUICC Engine 3x On-Chip NetworOn-Chip Networkk 2x PCI 4-ch. DMA4-ch. DMA Ethernet Gigabit QUICC Engine Express ControllerController 2x PCI 4-ch. DMA4-ch. DMA Ethernet Express ControllerController UTOPIA-L2 TDM Ethernet 4-lane SerDes 4-lane SerDes UTOPIA-L2 TDM Ethernet Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Basic Peripherals and Interconnect Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements Accelerators and Memory Control Networking ElementsThe P1012 and P1021 processors have an local storage. The integrated security engine Up to four HDLC interfaces with 128 advanced set of features for ease of use. can provide encrypted secure communications channels of HDLC The 256 KB L2 cache offers incremental for remote users with VPN support. Up to four BISYNC interfaces configuration to partition the cache between Up to four UART interfaces Technical Specifications the two cores or to configure it as SRAM or SPI interfaces stashing memory. GPIO Single (P1012) and dual (P1021) high- performance Power Architecture e500 High-speed USB controller (USB 2.0) Target Applications Host and device support cores The P1012 and P1021 processors serve a 36-bit physical addressing Enhanced host controller interface (EHCI) wide variety of applications and are well Double-precision floating-point suited for various combinations of data plane support ULPI interface to PHY Enhanced secure digital host controller and control plane workloads in networking 32 KB L1 instruction cache and 32 and telecom applications. With an available KB L1 data cache for each core Serial peripheral interface Integrated security engine (SEC 3.3) junction temperature range of 40 C to 533 MHz800 MHz core clock +125 C, the devices can be used in frequency Crypto algorithm support includes 3DES, AES, RSA/ECC, MD5/ powersensitive defense and industrial 256 KB L2 cache with ECC, also applications, and outdoor environments less configurable as SRAM and stashing SHA, ARC4, Snow 3G and FIPS deterministic RNG protected from the environment. The devices memory primarily target applications such as Three 10/100/1000 Mb/s enhanced three- Single pass encryption/message authentication for common security networking and telecom linecards. speed Ethernet controllers (eTSECs) TCP/IP acceleration and classification protocols (e.g., IPsec, SSL, SRTP, A multiservice router or business gateway WiMAX) capabilities requires a combination of high performance IEEE 1588 support XOR acceleration and a rich set of peripherals to support the 32-bit DDR2/DDR3 SDRAM memory Lossless flow control datapath throughputs and required system RGMII, SGMII controller with ECC support functionality. The P1012 and P1021 devices Programmable interrupt controller (PIC) High-speed interfaces (not all available offer a scalable platform to develop a range simultaneously) compliant with OpenPIC standard of products that can support the same Four-channel DMA controller Four SerDes to 3.125 GHz feature set. The QUICC Engine module, as 2 multiplexed across controllers Two I C controllers, DUART, timers well as integrated 10/100/1000 Ethernet Enhanced local bus controller (eLBC) Two PCI Express controllers controllers with classification and QoS Two SGMII interfaces 16 general-purpose I/O signals capabilities, are ideal for managing the Package: 689-pin wirebond power-BGA datapath traffic between the LAN and WAN QUICC Engine module (TEPBGA2) interface. PCI Express ports can provide UTOPIA-L2 connectivity to IEEE 802.11n radio cards for Up to two 10/100 Ethernet interfaces wireless support, TDM for legacy phone Up to four T1/E1/J1/E3 or DS-3 interfaces to support voice and the USB or serial interfaces SD/MMC interfaces can be used to support QorIQ P1021 Features QorIQ Device Cores Top Core L2 Size DDR 2/3 GE QUICC SerDes PCI Express Serial RapidIO TDM Platform Frequency Support Ports Engine P1 P1011 1 800 MHz 256 KB 32-bit with ECC 3 N/A 4 2 N/A Yes P1 P1020 2 800 MHz 256 KB 32-bit with ECC 3 N/A 4 2 N/A Yes P1 P1012 1 800 MHz 256 KB 32-bit with ECC 3 Yes 4 2 N/A In QUICC Engine P1 P1021 2 800 MHz 256 KB 32-bit with ECC 3 Yes 4 2 N/A In QUICC Engine P2 P2010 1 1200 MHz 512 KB 64-bit with ECC 3 N/A 4 3 2 N/A P2 P2020 2 1200 MHz 512 KB 64-bit with ECC 3 N/A 4 3 2 N/A For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine and CoreNet are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 2010, 2013, 2015 Freescale Semiconductor, Inc. Document Number: QORIQP1021FS REV 3