P3A9606JK 2 Dual bidirectional I3C/I C-bus and SPI voltage-level translator Rev. 1.0 10 May 2021 Product data sheet 1 General description The P3A9606JK is a 2-bit, dual supply translating transceiver with auto direction 2 sensing, that enables bidirectional voltage level translation for traditional I C-bus/SMBus applications, 12.5 MHz I3C-bus applications and also higher speed SPI applications (with two devices). It features two 1-bit input-output ports (An and Bn), one output enable input (OE) and two supply pins (V and V ). V can be supplied at any voltage between CCA CCB CCA 0.72 V and 1.98 V and V can be supplied at any voltage between 0.72 V and 1.98 V, CCB making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V and 1.8 V). V must be V to ensure proper operation. CCA CCB P3A9606JK can be used for both open drain as well as push-pull application which 2 allows for level translation applications using I3C, I C and SPI protocols. Pins An are referenced to V and pins Bn are referenced to V . The active HIGH CCA CCB OE pin is referenced to V and controllable by a signal in either V or V domain. CCA CCA CCB A LOW level at pin OE causes the outputs to be in a high-impedance OFF-state. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. 2 Features and benefits Wide supply voltage range: V : 0.72 V to 1.98 V and V : 0.72 V to 1.98 V V V CCA CCB CCA CCB I circuitry provides partial Power-down mode operation OFF Inputs accept voltages up to 1.98 V and are overvoltage tolerant to 1.98 V 2 Provided voltage level translation for I3C, I C-bus, SMBus and SPI devices ESD protection: HBM JESD22-A114E Class 2 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78B Class II Available in X2SON8 package Specified from -40 C to +85 C and -40 C to +125 CNXP Semiconductors P3A9606JK 2 Dual bidirectional I3C/I C-bus and SPI voltage-level translator 3 Ordering information Table 1.Ordering information Type number Topside Package marking Name Description Version 1 P3A9606JK Tx X2SON8 super thin small outline package, no leads 8 terminals SOT2015-1 0.35 mm pitch 1.35 mm x 1.0 mm x 0.32 mm body 1 changes based on date code. 3.1 Ordering options Table 2.Ordering options Type number Orderable part Package Packing method Minimum Temperature number order quantity P3A9606JK P3A9606JKZ X2SON8 Reel 13 Q1/T1 20000 T = -40 C to +125 C amb *standard mark SMD 1 with SSB 1 This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses. 4 Block diagram GATE CONTROL OE A1 B1 A2 B2 V V CCA CCB aaa-041094 Figure 1.Block diagram P3A9606JK All information provided in this document is subject to legal disclaimers. NXP B.V. 2021. All rights reserved. Product data sheet Rev. 1.0 10 May 2021 2 / 30