P82B96
Dual bidirectional bus buffer
Rev. 08 10 November 2009 Product data sheet
1. General description
The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface
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between the normal I C-bus and a range of other bus congurations. It can interface
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I C-bus logic signals to similar buses having different voltage and current levels.
For example, it can interface to the 350 A SMBus, to 3.3 V logic devices, and to 15 V
levels and/or low-impedance lines to improve noise immunity on longer bus lengths.
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It achieves this interface without any restrictions on the normal I C-bus protocols or clock
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speed. The IC adds minimal loading to the I C-bus node, and loadings of the new bus or
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remote I C-bus nodes are not transmitted or transformed to the local node. Restrictions
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on the number of I C-bus devices in a system, or the physical separation between them,
are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission
lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals may be directly
connected, without causing latching, to provide an alternative bidirectional signal line with
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I C-bus properties.
2. Features
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n Bidirectional data transfer of I C-bus signals
n Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side
n Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive
buses
n 400 kHz operation over at least 20 meters of wire (see AN10148)
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n Supply voltage range of 2 V to 15 V with I C-bus logic levels on Sx/Sy side
independent of supply voltage
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n Splits I C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths.
n Low power supply current
n ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V
SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up free (bipolar process with no latching structures)
n Packages offered: DIP8, SO8 and TSSOP8P82B96
NXP Semiconductors
Dual bidirectional bus buffer
3. Applications
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n Interface between I C-buses operating at different logic levels (for example, 5 V and
3 V or 15 V)
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n Interface between I C-bus and SMBus (350 A) standard
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n Simple conversion of I C-bus SDA or SCL signals to multi-drop differential bus
hardware, for example, via compatible PCA82C250
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n Interfaces with opto-couplers to provide opto-isolation between I C-bus nodes up to
400 kHz
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
P82B96DP TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-1
body width 3 mm
P82B96PN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
P82B96TD SO8 plastic small outline package; 8 leads; SOT96-1
body width 3.9 mm
P82B96TD/S900 SO8 plastic small outline package; 8 leads; SOT96-1
body width 3.9 mm
4.1 Ordering options
Table 2. Ordering options
Type number Topside mark Temperature range
P82B96DP 82B96 - 40 C to +85 C
P82B96PN P82B96PN - 40 C to +85 C
P82B96TD P82B96T - 40 C to +85 C
P82B96TD/S900 P82B96T - 40 C to +125 C
P82B96_8 NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 10 November 2009 2 of 32