P82B96 Dual bidirectional bus buffer Rev. 8.1 20 December 2021 Product data sheet 1 General description The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface 2 2 between the normal I C-bus and a range of other bus configurations. It can interface I C- bus logic signals to similar buses having different voltage and current levels. For example, it can interface to the 350 A SMBus, to 3.3 V logic devices, and to 15 V levels and/or low-impedance lines to improve noise immunity on longer bus lengths. 2 It achieves this interface without any restrictions on the normal I C-bus protocols or clock 2 speed. The IC adds minimal loading to the I C-bus node, and loadings of the new bus or 2 remote I C-bus nodes are not transmitted or transformed to the local node. Restrictions 2 on the number of I C-bus devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bidirectional signal line with 2 I C-bus properties. 2 Features 2 Bidirectional data transfer of I C-bus signals Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive buses 400 kHz operation over at least 20 meters of wire (see AN10148) 2 Supply voltage range of 2 V to 15 V with I C-bus logic levels on Sx/Sy side independent of supply voltage 2 Splits I C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths. Low power supply current ESD protection exceeds 3500 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 Latch-up free (bipolar process with no latching structures) Packages offered: SO8 and TSSOP8 3 Applications 2 Interface between I C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V) 2 Interface between I C-bus and SMBus (350 A) standardNXP Semiconductors P82B96 Dual bidirectional bus buffer 2 Simple conversion of I C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250 2 Interfaces with opto-couplers to provide opto-isolation between I C-bus nodes up to 400 kHz 4 Ordering information Table 1.Ordering information Type number Topside Package marking Name Description Version P82B96DP 82B96 TSSOP8 plastic thin shrink small outline package 8 leads body width 3 SOT505-1 mm P82B96TD P82B96T SO8 plastic small outline package 8 leads body width 3.9 mm SOT96-1 P82B96TD/S900 P82B96T SO8 plastic small outline package 8 leads body width 3.9 mm SOT96-1 4.1 Ordering options Table 2.Ordering options 1 Type number Orderable part Package Packing method Minimum Temperature number order quantity 2 3 P82B96DP P82B96DPZ TSSOP8 REEL 13 Q1/T1 NDP SSB 2500 T = -40 C to +85 C amb P82B96DP,118 TSSOP8 REEL 13 Q1/T1 NDP 2500 T = -40 C to +85 C amb P82B96TD P82B96TD,118 SO8 REEL 13 Q1/T1 NDP 2500 T = -40 C to +85 C amb P82B96TD/S900 P82B96TD/S900,118 SO8 REEL 13 Q1/T1 NDP 2500 T = -40 C to +125 C amb 1 Standard packing quantities and other packaging data are available at www.nxp.com/packages/. 2 Orderable part number P82B96DPZ is a drop in alternate for P82B96DP,118. 3 This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in sealed bag between uses. 5 Block diagram V (2 V to 15 V) CC 8 P82B96 1 3 Sx (SDA) Tx (TxD, SDA) 2 Rx (RxD, SDA) 5 7 Sy (SCL) Ty (TxD, SCL) 6 Ry (RxD, SCL) 4 GND 002aab976 Figure 1.Block diagram of P82B96 P82B96 All information provided in this document is subject to legal disclaimers. NXP B.V. 2021. All rights reserved. Product data sheet Rev. 8.1 20 December 2021 2 / 32