PBSS5230QA NXP

PBSS5230QA 30 V, 2 A PNP low VCEsat (BISS) transistor 23 August 2013 Product data sheet 1. General description PNP low V Breakthrough In Small Signal (BISS) transistor in a leadless ultra small CEsat DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads. NPN complement: PBSS4230QA. 2. Features and benefits Very low collector-emitter saturation voltage V CEsat High collector current capability I and I C CM High collector current gain h at high I FE C High energy efficiency due to less heat generation Reduced Printed-Circuit Board (PCB) area requirements Solderable side pads AEC-Q101 qualified 3. Applications Loadswitch Battery-driven devices Power management Charging circuits Power switches (e.g. motors, fans) 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V collector-emitter open base - - -30 V CEO voltage I collector current - - -2 A C I peak collector current t 1 ms pulsed - - -3 A CM p R collector-emitter I = -1 A I = -100 mA pulsed - 120 180 m CEsat C B saturation resistance t 300 s 0.02 T = 25 C p amb Scan or click this QR code to view the latest information for this product DFN1010D-3NXP Semiconductors PBSS5230QA 30 V, 2 A PNP low VCEsat (BISS) transistor 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 B base C 1 2 E emitter B 3 C collector 4 3 E sym132 4 C collector 2 Transparent top view DFN1010D-3 (SOT1215) 6. Ordering information Table 3. Ordering information Type number Package Name Description Version PBSS5230QA DFN1010D-3 plastic thermal enhanced ultra thin small outline package no SOT1215 leads 3 terminals 7. Marking Table 4. Marking codes Type number Marking code PBSS5230QA 00 00 10 READING DIRECTION MARKING CODE (EXAMPLE) YEAR DATE CODE VENDOR CODE PIN 1 MARK-FREE AREA INDICATION MARK READING EXAMPLE: 11 01 10 aaa-008041 Fig. 1. DFN1010D-3 (SOT1215) binary marking code description PBSS5230QA All information provided in this document is subject to legal disclaimers. NXP N.V. 2013. All rights reserved Product data sheet 23 August 2013 2 / 17