PC9RS08LA8CLF NXP

Freescale Semiconductor Document Number: MC9RS08LA8 Rev. 2, 1/2012 Data Sheet: Technical Data MC9RS08LA8 48 QFN 48 LQFP Case 1975 Case 932 TBD 2 2 7 mm 7 mm MC9RS08LA8 Features: LCD Up to 8 21 or 4 25 segments compatible with 5 V or 3 V LCD glass displays using on-chip charge 8-Bit RS08 Central Processor Unit (CPU) pump functional in wait, stop modes for very low power Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature LCD operation frontplane and backplane pins range of 40C to 85C multiplexed with GPIO functions selectable frontplane Subset of HC08 instruction set with added BGND and backplane configurations instruction ADC 6-channel, 10-bit resolution 2.5 s conversion On-Chip Memory time automatic compare function 1.7 mV/C 8 KB flash read/program/erase over full operating temperature sensor internal bandgap reference channel voltage and temperature operation in stop fully functional from 2.7 V to 5.5 V. 256-byte random-access memory (RAM) TPM One 2-channel 16-bit timer/pulse-width Security circuitry to prevent unauthorized access to flash modulator (TPM) module contents SCI One 2-channel serial communications interface Power-Saving Modes module with optional 13-bit break LIN extensions Wait and stop SPI One serial peripheral interface module in 8-bit Clock Source Options data length mode with a receive data buffer hardware Oscillator (XOSC) Loop-control Pierce oscillator match function crystal or ceramic resonator range of 31.25 kHz to ACMP Analog comparator with option to compare to 39.0625 kHz or 1 MHz to 16 MHz internal reference Internal clock source (ICS) Internal clock source MTIM One 8-bit modulo timer module containing a frequency-locked-loop (FLL) KBI 8-pin keyboard interrupt module controlled by internal or external reference supports bus RTI One real-time interrupt module with optional frequencies up to 10 MHz reference clock. System Protection Input/Output Watchdog computer operating properly (COP) reset 33 GPIOs including 1 output only pin and 1 input only with option to run from dedicated 1 kHz internal clock pin. source or bus clock Hysteresis and configurable pullup device on all input Low-voltage detection with reset or interrupt selectable pins configurable slew rate and drive strength on all trip points output pins. Illegal opcode detection with reset Package Options Illegal address detection with reset 48-pin QFN Flash block protection 48-pin LQFP Development Support Single-wire background debug interface Breakpoint capability to allow single breakpoint setting during in-circuit debugging Peripherals This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2008-2012. All rights reserved.Table of Contents 1 MCU Block Diagram .3 3.8.1 Control Timing . 17 2 Pin Assignments 4 3.8.2 TPM/MTIM Module Timing 18 3 Electrical Characteristics .7 3.9 Analog Comparator (ACMP) Electrical 19 3.1 Parameter Classification .7 3.10 Internal Clock Source Characteristics . 19 3.2 Absolute Maximum Ratings 7 3.11 ADC Characteristics 20 3.3 Thermal Characteristics .8 3.12 AC Characteristics 22 3.4 ESD Protection and Latch-Up Immunity .9 3.12.1 Control Timing . 22 3.5 DC Characteristics 10 3.13 Flash Specifications . 23 3.6 Supply Current Characteristics .14 4 Ordering Information . 25 3.7 External (XOSC) and Internal (ICS) Oscillator 5 Package Information and Mechanical Drawings 26 Characteristics .15 3.8 AC Characteristics 17 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: