PCA9510A 2 Hot swappable I C-bus and SMBus bus buffer Rev. 04 18 August 2009 Product data sheet 1. General description 2 The PCA9510A is a hot swappable I C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9510A provides bidirectional buffering, keeping the backplane and card capacitances isolated. The PCA9510A has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a Low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW). During insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip. Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side or P82B96 Sx/y side. 2. Features n Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems 2 2 n Compatible with Standard-mode I C-bus, Fast-mode I C-bus, and SMBus standards n Active HIGH ENABLE input n Active HIGH READY open-drain output n High-impedance SDAn and SCLn pins for V =0V CC n 1 V precharge on SDAIN and SCLIN inputs n Supports clock stretching and multiple master arbitration and synchronization n Operating power supply voltage range: 2.7 V to 5.5 V n 5 V tolerant I/Os n 0 Hz to 400 kHz clock frequency n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: SO8, TSSOP8 (MSOP8)PCA9510A NXP Semiconductors 2 Hot swappable I C-bus and SMBus bus buffer 3. Applications n cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system 4. Feature selection Table 1. Feature selection chart Feature PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A Idle detect yes yes yes yes yes High-impedance SDA, SCL pins for V = 0 V yes yes yes yes yes CC Rise time accelerator circuitry on SDAn and SCLn pins - yes yes yes yes Rise time accelerator circuitry hardware disable pin for--yes -- lightly loaded systems Rise time accelerator threshold 0.8 V versus 0.6 V ---yes yes improves noise margin Ready open-drain output yes yes - yes yes Two V pins to support 5 V to 3.3 V level translation with--yes -- CC improved noise margins 1 V precharge on all SDAn and SCLn pins in only yes yes - - 92 A current source on SCLIN and SDAIN for PICMG---yes - applications 5. Ordering information Table 2. Ordering information T = - 40 C to +85 C. amb Type number Topside Package mark Name Description Version PCA9510AD PA9510A SO8 plastic small outline package 8 leads body width 3.9 mm SOT96-1 1 PCA9510ADP 9510A TSSOP8 plastic thin shrink small outline package 8 leads body width 3 mm SOT505-1 1 Also known as MSOP8. PCA9510A 4 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 18 August 2009 2 of 24